MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 3
![KIT DEVELOPMENT I.MX53](/photos/39/51/395134/4751369_sml.jpg)
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 3 of 180
- Download datasheet (2Mb)
1.1
Table 1
1.2
The i.MX53xA multimedia applications processor (AP) is based on the ARM Platform, which has the
following features:
The memory system consists of the following components:
Freescale Semiconductor
1
PCIMX536AVV8B
Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.
•
•
•
•
•
•
•
•
•
Part Number
MMU, L1 instruction and L1 data cache
Unified L2 cache
Target frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz
Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)
coprocessor supporting VFPv3
TrustZone
Level 1 cache:
— Instruction (32 Kbyte)
— Data (32 Kbyte)
Level 2 cache:
— Unified instruction and data (256 Kbyte)
Level 2 (internal) memory:
— Boot ROM, including HAB (64 Kbyte)
— Internal multimedia/shared, fast access RAM (128 Kbyte)
— Secure/non-secure RAM (16 Kbyte)
External memory interfaces:
— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte
— 32bit LPDDR2
— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC
— 8,16-bit NOR Flash, PSRAM & cellular RAM.
— 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.
— 8-bit Asynchronous (DTACK mode) EIM interface.
provides ordering information.
Ordering Information
Features
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Mask
N78C
Set
800 MHz, full feature set
Table 1. Ordering Information
Features
—
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
Package
1
Introduction
3
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