MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 89
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MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 57
Freescale Semiconductor
IP5
IP6
IP7
IP8
IP9
IP10
IP12
IP13
IP14
IP15
ID
Display interface clock period
Display pixel clock period
Screen width time
HSYNC width time
Horizontal blank interval 1
Horizontal blank interval 2
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
shows timing characteristics of signals presented in
Table 57. Synchronous Display Interface Timing Characteristics (Pixel Level)
Parameter
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Symbol
Tdpcp
Thbi1
Thbi2
Tdicp
Tvbi1
Tvbi2
Thsw
Tvsw
Tsw
Tsh
DISP_CLK_PER_PIXEL
(SCREEN_HEIGHT –
BGXP – FW)
(SCREEN_WIDTH –
(SCREEN_HEIGHT)
(SCREEN_WIDTH)
BGYP – FH)
(HSYNC_WIDTH)
VSYNC_WIDTH
BGXP
BGYP
×
×
×
Value
Tdicp
Tdicp
(
Tsw
1
×
)
×
Tdicp
Tsw
×
×
Tdicp
Tsw
Figure 46
Display interface clock.
Time of translation of one pixel to display,
DISP_CLK_PER_PIXEL—number of pixel
components in one pixel (1.n). The
DISP_CLK_PER_PIXEL is virtual
parameter to define Display pixel clock
period.
The DISP_CLK_PER_PIXEL is received by
DC/DI one access division to n
components.
SCREEN_WIDTH—screen width in,
interface clocks. horizontal blanking
included.
The SCREEN_WIDTH should be built by
suitable DI’s counter
HSYNC_WIDTH—Hsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
BGXP—width of a horizontal blanking
before a first active data in a line (in
interface clocks). The BGXP should be built
by suitable DI’s counter.
Width a horizontal blanking after a last
active data in a line (in interface clocks)
FW—with of active line in interface clocks.
The FW should be built by suitable DI’s
counter.
SCREEN_HEIGHT— screen height in lines
with blanking.
The SCREEN_HEIGHT is a distance
between 2 VSYNCs.
The SCREEN_HEIGHT should be built by
suitable DI’s counter.
VSYNC_WIDTH—Vsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter
BGYP—width of first Vertical
blanking interval in line.The BGYP should
be built by suitable DI’s counter.
Width of second Vertical
blanking interval in line.The FH should be
built by suitable DI’s counter.
and
Description
Figure
2
.
Electrical Characteristics
IPP_DISP_CLK
47.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
89
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