MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 130
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Electrical Characteristics
4.7.17
This section describes the timing parameters of the SSI module. The connectivity of the serial
synchronous interfaces are summarized in
130
(Output)
STCLK
(Input)
SRCK
SSI Timing Parameters
•
•
AUDMUX port 1
AUDMUX port 2
AUDMUX port 3
AUDMUX port 4
AUDMUX port 5
AUDMUX port 6
AUDMUX port 7
The terms WL and BL used in the timing diagrams and tables refer to
Word Length (WL) and Bit Length (BL).
The SSI timing diagrams use generic signal names wherein the names
used in the i.MX53 reference manual are channel specific signal names.
For example, a channel clock referenced in the IOMUXC chapter as
AUD3_TXC appears in the timing diagram as TXC.
Port
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Signal Nomenclature
Table 81. AUDMUX Port Allocation
Figure 83. SPDIF Timing Diagram
AUD3
AUD4
AUD5
AUD6
SSI 1
SSI 2
SSI 3
Figure 84. STCLK Timing
stclkpl
srckpl
Table
V
V
M
M
81.
NOTE
Internal
Internal
External – AUD3 I/O
External – EIM or CSPI1 I/O through IOMUXC
External – EIM or SD1 I/O through IOMUXC
External – EIM or DISP2 through IOMUXC
Internal
stclkp
srckp
Type and Access
stclkph
srckph
V
V
M
M
Freescale Semiconductor
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