LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 6

• Manufacturer Part Number: LFXP2-8E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 Memory Usage Guide
Dynamic Phase Adjustment/Duty Cycle Select.................................................................................................. 9-9
PLL Usage in IPexpress™ ............................................................................................................................... 9-10
PLL Modes of Operation .................................................................................................................................. 9-13
IPexpress Output ............................................................................................................................................. 9-14
Use of the Pre-Map Preference Editor ............................................................................................................. 9-15
Clock Dividers (CLKDIV).................................................................................................................................. 9-15
DCS (Dynamic Clock Select) ........................................................................................................................... 9-19
Power Supplies ................................................................................................................................................ 9-23
Technical Support Assistance.......................................................................................................................... 9-23
Revision History ............................................................................................................................................... 9-23
Appendix A. Primary Clock Sources and Distribution ...................................................................................... 9-24
Appendix B. PLL, CLKDIV and ECLK Locations and Connectivity .................................................................. 9-25
Appendix C. Clock Preferences ....................................................................................................................... 9-26
Introduction ...................................................................................................................................................... 10-1
Memories in LatticeXP2 Devices ..................................................................................................................... 10-1
Utilizing IPexpress............................................................................................................................................ 10-2
Memory Modules.............................................................................................................................................. 10-6
EPLLD Design Migration from LatticeECP2 to LatticeXP2 ....................................................................... 9-8
Dynamic Phase/Duty Mode....................................................................................................................... 9-8
Configuration Tab.................................................................................................................................... 9-11
PLL Clock Injection Removal .................................................................................................................. 9-13
PLL Clock Phase Adjustment.................................................................................................................. 9-14
CLKDIV Primitive Definition .................................................................................................................... 9-15
CLKDIV Declaration in VHDL Source Code............................................................................................ 9-16
CLKDIV Usage with Verilog - Example ................................................................................................... 9-17
CLKDIV Example Circuits ....................................................................................................................... 9-17
Reset Behavior........................................................................................................................................ 9-18
Release Behavior.................................................................................................................................... 9-18
CLKDIV Inputs-to-Outputs Delay Matching............................................................................................. 9-19
DCS Primitive Definition.......................................................................................................................... 9-19
DCS Timing Diagrams ............................................................................................................................ 9-20
DCS Usage with VHDL - Example .......................................................................................................... 9-21
DCS Usage with Verilog - Example ........................................................................................................ 9-22
Oscillator (OSCE).................................................................................................................................... 9-22
OSC Primitive Symbol (OSCE) ............................................................................................................... 9-22
OSC Usage with VHDL - Example.......................................................................................................... 9-23
OSC Usage with Verilog - Example ........................................................................................................ 9-23
Setting Clock Preferences....................................................................................................................... 9-23
ASIC........................................................................................................................................................ 9-26
FREQUENCY.......................................................................................................................................... 9-26
MAXSKEW.............................................................................................................................................. 9-26
MULTICYCLE ......................................................................................................................................... 9-26
PERIOD .................................................................................................................................................. 9-26
PROHIBIT ............................................................................................................................................... 9-26
USE PRIMARY ....................................................................................................................................... 9-26
USE SECONDARY ................................................................................................................................. 9-26
USE EDGE.............................................................................................................................................. 9-27
CLOCK_TO_OUT ................................................................................................................................... 9-27
INPUT_SETUP ....................................................................................................................................... 9-27
PLL_PHASE_BACK................................................................................................................................ 9-27
IPexpress Flow........................................................................................................................................ 10-3
Single Port RAM (RAM_DQ) – EBR Based ............................................................................................ 10-6
True Dual Port RAM (RAM_DP_TRUE) – EBR Based ......................................................................... 10-11
5
LatticeXP2 Family Handbook
Table of Contents