LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 179

• Manufacturer Part Number: LFXP2-8E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Let us assume that we start to write into the FIFO_DC to fill it. The write operation is controlled by WrClock and
WrEn, however it takes extra RdClock cycles for de-assertion of the Empty and Almost Empty flags.
On the other hand, de-assertion of Full and Almost Full result in the reading out of the data from the FIFO_DC. It
takes extra WrClock cycles, after reading this data, for the flags to come out.
With this in mind, let us look at the FIFO_DC without output registers waveforms. Figure 10-30 shows the operation
of the FIFO_DC when it is empty and the data starts to be written into it.
Figure 10-30. FIFO_DC without Output Registers, Start of Data Write Cycle
The WrEn signal must be high to start writing into the FIFO_DC. The Empty and Almost Empty flags are high to
begin and Full and Almost full are low.
When the first data is written into the FIFO_DC, the Empty flag de-asserts (or goes low), as the FIFO_DC is no lon-
ger empty. In this figure we assume that the Almost Empty setting flag setting is 3 (address location 3). So the
Almost Empty flag is de-asserted when the third address location is filled.
Now let us assume that we continue to write into the FIFO_DC to fill it. When the FIFO_DC is filled, the Almost Full
and Full Flags are asserted. Figure 10-31 shows the behavior of these flags. In this figure the FIFO_DC depth is
'N'.
RPReset
WrClock
RdClock
Almost
Almost
Empty
Empty
Reset
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
10-29
Invalid Q
Data_3
Data_4
LatticeXP2 Memory Usage Guide
Data_5