LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 118

• Manufacturer Part Number: LFXP2-8E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Verilog Synplicity
This section lists syntax and examples for all the sysIO Attributes in Verilog using the Synplicity synthesis tool.
Syntax
Table 8-13. Verilog Synplicity Attribute Syntax
Examples
//IO_TYPE, PULLMODE, SLEWRATE and DRIVE assignment
output portB /*synthesis IO_TYPE=”LVCMOS33” PULLMODE =”UP” SLEWRATE =”FAST”
DRIVE =”20”*/;
output portC /*synthesis IO_TYPE=”LVDS25” */;
//OPENDRAIN
output portA /*synthesis OPENDRAIN =”ON”*/;
//PCICLAMP
output portA /*synthesis IO_TYPE=”PCI33” PULLMODE =”PCICLAMP”*/;
// Fixeddelay
input load /* synthesis FIXEDDELAY=”TRUE” */;
// Place the flip-flops near the load input
input load /* synthesis din=”” */;
// Place the flip-flops near the outload output
output outload /* synthesis dout=”” */;
//I/O pin location
input [3:0] DATA0 /* synthesis loc=”E3,B1,F3”*/;
//Register pin location
reg data_in_ch1_buf_reg3 /* synthesis loc=”R40C47” */;
//Vectored internal bus
reg [3:0] data_in_ch1_reg /*synthesis loc =”R40C47,R40C46,R40C45,R40C44” */;
IO_TYPE
OPENDRAIN
DRIVE
PULLMODE
PCICLAMP
SLEWRATE
FIXEDDELAY
DIN
DOUT
LOC
Attribute
PinType PinName /* synthesis IO_TYPE=”IO_Type Value”*/;
PinType PinName /* synthesis OPENDRAIN =”OpenDrain Value”*/;
PinType PinName /* synthesis DRIVE=”Drive Value”*/;
PinType PinName /* synthesis PULLMODE=”Pullmode Value”*/;
PinType PinName /* synthesis PCICLAMP =” PCIClamp Value”*/;
PinType PinName /* synthesis SLEWRATE=”Slewrate Value”*/;
PinType PinName /* synthesis FIXEDDELAY=”Fixeddelay Value”*/;
PinType PinName /* synthesis DIN=” “*/;
PinType PinName /* synthesis DOUT=” “*/;
PinType PinName /* synthesis LOC=”pin_locations “*/;
8-14
Syntax
LatticeXP2 sysIO Usage Guide