LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 223

• Manufacturer Part Number: LFXP2-8E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Data Read Critical Path
Data in the second stage DDR registers can be registered either on the positive edge or on the falling edge of
FPGA clock depending on the DDRCLKPOL signal. In order to ensure that the data transferred to the FPGA core
registers is aligned to the rising edge of the system clock, this path should be constrained with a half clock transfer.
This half clock transfer can be forced in the software by assigning a multi-cycle constraint (multi-cycle of 0.5 X) on
all the data paths to first PFU register.
DQS Postamble
At the end of a READ cycle, the DDR SDRAM device executes the READ cycle postamble and then immediately
tristates both the DQ and DQS output drivers. Since neither the memory controller (FPGA) nor the DDR SDRAM
device are driving DQ or DQS at that time, these signals float to a level determined by the off-chip termination
resistors. While these signals are floating, noise on the DQS strobe may be interpreted as a valid strobe signal by
the FPGA input buffer. This can cause the last READ data captured in the IOL input DDR registers to be overwrit-
ten before the data has been transferred to the free running resynchronization registers inside the FPGA.
Figure 11-23. Postamble Effect on READ
LatticeXP2 devices have extra dedicated logic in the in the DQS Delay Block that prevents this postamble problem.
The DQS postamble logic is automatically implemented when the user instantiates the DQS Delay logic (DQS-
BUFC software primitive) in the design.
Memory Write Implementation
To implement the write portion of a DDR memory interface, two streams of single data rate data must be multi-
plexed together with data transitioning on both edges of the clock. In addition, during a write cycle, DQS must arrive
at the memory pins center-aligned with the data, DQ. Along with the DQS strobe and data this portion of the inter-
face must also provide the CLKP, CLKN Address/Command and Data Mask (DM) signals to the memory.
It is the responsibility of the FPGA output control to edge-align the DDR output signals (ADDR,CMD, DQS, but not
DQ, DM) to the rising edge of the outgoing differential clock (CLKP/CLKN).
Challenges encountered by the during Memory WRITE:
1. DQS needs to be center-aligned with the outgoing DDR Data, DQ.
2. Differential CLK signals (CLKP and CLKN) need to be generated.
DQS at PIN
DQS at IOL
DATAIN_N
DATAIN_P
DQ at PIN
DQ at IOL
synce reg
CLK at
C
A
B
P0
P0
11-19
P0
N0
N0
P1
P1
LatticeXP2 High-Speed I/O Interface
N0
P0
P0
N0
P1
N1
N1
N1
P1