LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 263

• Manufacturer Part Number: LFXP2-8E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Lattice XP2 sysDSP Usage Guide
MAC Module
The MAC Module configures multiply accumulate elements to be packed into the primitive MULT18X18MACB. The
Basic mode, shown in Figure 13-4, consists of an optional one clock, one clock enable and one reset tied to all reg-
isters. Because of the accumulator, the output register is automatically enabled. Multiple sysDSP Blocks can be
spanned to accommodate large multiplications. The accumulator of the sysDSP block is 52 bits deep and addi-
tional LUTs can be used if a larger accumulation is required. If sysDSP blocks are spanned, additional LUT logic
may be required. Select Area/Speed to determine the LUT implementation. The input data format can be selected
as Parallel, Shift or Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The Shift format
enables a sample/shift register. The Accumsload loads the accumulator with the value from the LD port. This is
required to initialize and load the first value of the accumulation. The Advanced mode, shown in Figure 13-5, allows
finer control over the registers. In the advanced mode, users can control each register with independent clocks,
clock enables and resets. MAC inputs can be from 2 to 72 bits.
Figure 13-4. MAC Mode Basic Set-up
13-4