SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet - Page 44

• Manufacturer Part Number: SPEAR300-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR300-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr300
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 56 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10849-5

Table 11.
PL_GPIO_51/D10
PL_GPIO_50/A12
PL_GPIO_49/C11
PL_GPIO_48/B11
PL_GPIO_47/C10
PL_GPIO_46/A11
PL_GPIO_45/B10
PL_GPIO_44/A10
PL_GPIO_# /
PL_GPIO_42/D9
PL_GPIO_41/C9
PL_GPIO_36/C8
PL_GPIO_35/D8
PL_GPIO_32/D7
PL_GPIO_31/C7
PL_GPIO_43/E9
PL_GPIO_40/B9
PL_GPIO_39/A9
PL_GPIO_38/A8
PL_GPIO_37/B8
PL_GPIO_34/E8
PL_GPIO_33/E7
ball number
PL_GPIO multiplexing scheme (continued)
Reserved Reserved TDM_CLK
B0
B1
B2
B3
H0
H1
H2
H3
H4
H5
H6
H7
1
0
0
0
0
0
0
0
0
H0
H1
H2
H3
H4
H5
H6
H7
B0
B1
B2
B3
2
0
0
0
0
0
0
0
0
TDM_DIN
SD_DAT0
SD_CMD
SD_CLK
SYNC1
SYNC0
CLD22
CLD23
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
TDM_
TDM_
DOUT
TDM_
CLPP
CLLP
CLLE
3
TDM_ DOUT
I2S_ DOUT
I2S_ LRCK
TDM_CLK
TDM_DIN
SPI_I2C0
SPI_I2C1
SPI_I2C2
SPI_I2C3
SD_CMD
SD_DAT0
I2S_CLK
DAC_O0
DAC_O1
I2S_DIN
SD_CLK
G10_3/
G10_2/
SYNC1
SYNC0
G10_6
G10_5
G10_4
TDM_
TDM_
4
Configuration mode (enabled by RAS register 2)
TDM_CLK TDM_CLK TDM_CLK TDM_CLK TDM_CLK TDM_CLK
TDM_DIN
SPI_I2C0
SPI_I2C1
SPI_I2C2
SPI_I2C3
SD_CMD
SD_DAT0
I2S_CLK
DAC_O0
DAC_O1
I2S_DIN
SD_CLK
SYNC1
SYNC0
G10_3/
G10_2/
LRCK
DOUT
TDM_
TDM_
DOUT
TDM_
CLLP
CLLE
CLPP
I2S_
I2S_
5
TDM_DIN
SD_DAT0
SPI_I2C0
SPI_I2C1
SPI_I2C2
SPI_I2C3
SD_CMD
DAC_O0
DAC_O1
I2S_CLK
I2S_DIN
SD_CLK
G10_3/
G10_2/
SYNC1
SYNC0
G10_6
G10_5
G10_4
DOUT
DOUT
LRCK
TDM_
TDM_
TDM_
I2S_
I2S_
6
TDM_DIN
SD_DAT0
SPI_I2C0
SPI_I2C1
SPI_I2C2
SPI_I2C3
SD_CMD
DAC_O0
DAC_O1
I2S_CLK
SD_CLK
I2S_DIN
G10_3/
G10_2/
SYNC1
SYNC0
DOUT
DOUT
CLPP
LRCK
TDM_
TDM_
TDM_
CLLP
CLLE
I2S_
I2S_
7
TDM_DIN
SD_DAT0
SPI_I2C0
SPI_I2C1
SPI_I2C2
SPI_I2C3
SD_CMD
TDM_SY
TDM_SY
SD_CLK
SYNC1
SYNC0
G10_6
G10_5
G10_4
G10_3
G10_2
G10_1
G10_0
DOUT
TDM_
TDM_
TDM_
NC3
NC2
8
SPI_I2C0
SPI_I2C1
SPI_I2C2
SPI_I2C3
TDM_DIN
SD_DAT0
I2S_LRC
SD_CMD
DAC_O0
DAC_O1
I2S_CLK
SD_CLK
I2S_DIN
SYNC1
SYNC0
G10_6
G10_5
G10_4
DOUT
TDM_
TDM_
DOUT
TDM_
9
K
I2S_DOUT I2S_DOUT I2S_DOUT I2S_DOUT
I2S_LRCK I2S_LRCK I2S_LRCK I2S_LRCK
TDM_DIN
SPI_I2C0
SPI_I2C1
SPI_I2C2
SPI_I2C3
SD_CMD
SD_DAT0
I2S_CLK
DAC_O0
DAC_O1
I2S_DIN
SD_CLK
SYNC1
SYNC0
G10_6
G10_5
G10_4
TDM_
TDM_
DOUT
TDM_
10
TDM_CLK
TDM_DIN
SD_CMD
SD_DAT0
I2S_CLK
DAC_O0
DAC_O1
I2S_DIN
SD_CLK
DIO4_1
DIO5_1
DIO6_1
DIO7_1
SYNC1
SYNC0
TDM_
TDM_
DOUT
TDM_
CLLP
CLLE
CLPP
11
TDM_CLK
TDM_DIN
SD_DAT0
SD_CMD
DAC_O0
DAC_O1
I2S_CLK
I2S_DIN
SD_CLK
DIO4_1
DIO5_1
DIO6_1
DIO7_1
SYNC1
SYNC0
G10_6
G10_5
G10_4
DOUT
TDM_
TDM_
TDM_
12
TDM_CLK
TDM_DIN
SD_DAT0
SPI_I2C0
SPI_I2C1
SPI_I2C2
SPI_I2C3
SD_CMD
DAC_O0
DAC_O1
I2S_CLK
SD_CLK
I2S_DIN
SYNC1
SYNC0
DOUT
CLPP
TDM_
TDM_
TDM_
CLLP
CLLE
13
register 1)
TMR_CPTR4
TMR_CPTR3
TMR_CPTR2
TMR_CPTR1
Alternate
(enabled
TMR_CLK4
TMR_CLK3
TMR_CLK2
TMR_CLK1
UART_DTR
UART_DSR
UART_DCD
UART_CTS
UART_RTS
function
BasGPIO5
BasGPIO4
BasGPIO3
by RAS
SSP_CS4
SSP_CS3
SSP_CS2
UART_RI