SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet - Page 17

• Manufacturer Part Number: SPEAR300-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR300-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr300
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 56 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10849-5

SPEAr300
2.11
2.12
2.13
Flexible static memory controller (FSMC)
SPEAr300 provides a Flexible Static Memory Controller (FSMC) which interfaces the AHB
bus to external NAND/NOR Flash memories and to asynchronous SRAM memories.
Main features:
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UART
Main features:
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Fast IrDA controller (FIrDA)
The fast IrDA controller is a programmable infrared controller that acts as an interface to an
off-chip infrared transceiver. This controller is able to perform the modulation and the
demodulation of the infrared signals and the wrapping of the IrDA link access protocol
(IrLAP) frames.
Provides an interface between AHB system bus and external parallel memory devices
Interfaces static memory-mapped devices including RAM, ROM and synchronous burst
Flash.
For SRAM and Flash 8/16-bit wide, external memory and data paths are provided
FSMC performs only one access at a time and only one external device is accessed.
Supports little-endian and big-endian memory architectures
AHB burst transfer handling to reduce access time to external devices
Supplies an independent configuration for each memory bank
Programmable timings to support a wide range of devices
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Provides independent chip select control for each memory bank
Shares the address bus and the data bus with all the external peripherals. Only the chip
selects are unique for each peripheral
External asynchronous wait control
Hardware/software flow control
Modem control signals
Separate 16 x 8 (16 locations deep x 8-bit wide) transmit and 16 x 12 receive FIFOs to
reduce CPU interrupts
Speed up to 3 Mbps.
Programmable wait states (up to 31)
Programmable bus turnaround cycles (up to 15)
Programmable output enable and write enable delays (up to 15)
Doc ID 16324 Rev 2
Architecture overview
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