SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet - Page 22

• Manufacturer Part Number: SPEAR300-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR300-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr300
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 56 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10849-5

Architecture overview
2.20
2.21
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Keyboard controller
SPEAr300 provides a GPIO/keyboard controller block which is a two-mode input and output
port.
Main features:
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CLCD controller
SPEAr300 has a color liquid crystal display controller (CLCDC) that provides all the
necessary control signals to interface directly to a variety of color and monochrome LCD
panels.
Main features:
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The selection between the two modes is an APB Bus programmable bit.
Keyboard interface uses 18 pins
18-bit general-purpose parallel port with input or output single pin programmability
Pins can be used as general purpose I/O or to drive a 9 x 9 keyboard (81 keys)
Keyboard scan period can be adjusted between 10 ms and 80 ms
Supports auto-scanning with debouncing.
Resolution programmable up to 1024 x 768
16-bpp true-color non-palletized, for color STN and TFT
24-bpp true-color non-palletized, for color TFT
Supports single and dual panel mono super twisted nematic (STN) displays with 4 or 8-
bit interfaces
Supports single and dual-panel color and monochrome STN displays
Supports thin film transistor (TFT) color displays
15 gray-level mono, 3375 color STN, and 32 K color TFT support
1, 2, or 4 bits per pixel (bpp) palletized displays for mono STN
1, 2, 4 or 8-bpp palletized color displays for color STN and TFT
Programmable timing for different display panels
256 entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM physically frame, line
and pixel clock signals
AC bias signal for STN and data enable signal for TFT panels patented gray scale
algorithm
Supports little and big-endian
Doc ID 16324 Rev 2
SPEAr300