SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet
SPEAR300-2
Specifications of SPEAR300-2
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SPEAR300-2 Summary of contents
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... Flash based devices – Digital photo frames – WiFi or IP phones (low end or high end) – ATA PABX systems (with or without I – 8-bit or 14-bit camera (with or without LCD) Table 1. Order code SPEAR300 °C Doc ID 16324 Rev 2 SPEAr300 LFBGA289 ( 1.7 mm) Device summary Temp Package range, ...
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... TDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.19 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.20 Keyboard controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.21 CLCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.22 Camera interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.23 SDIO controller/MMC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.24 Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.25 USB2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/83 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Doc ID 16324 Rev 2 SPEAr300 ...
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... SPEAr300 2.26 USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.27 JPEG (CODEC 2.28 Cryptographic co-processor (C3 2.29 8-channel ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.30 1-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1 Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 Dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 Shared I/O pins (PL_GPIOs 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.4 PL_GPIO pin sharing for debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4 Memory mapping ...
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... CLCD timing characteristics direct clock . . . . . . . . . . . . . . . . . . . . . . . . 60 CLCD timing characteristics divided clock . . . . . . . . . . . . . . . . . . . . . . . 61 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 MII receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 MDIO timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SPI master mode timings (clock phase = SPI master mode timings (clock phase = Doc ID 16324 Rev 2 SPEAr300 ...
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... SPEAr300 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Master clock, RTC, Reset and 3.3 V comparator pin descriptions . . . . . . . . . . . . . . . . . . 29 Table 3. Power supply pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 4. Debug pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5. Serial memory interface (SMI) pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6. USB pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 7. ADC pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 8. ...
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... Table 48. Switching characteristics over recommended operating conditions for SPI master mode (clock phase = Table 49. UART transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 50. UART receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 51. LFBGA289 ( 1.7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 52. Thermal resistance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 53. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6/83 Doc ID 16324 Rev 2 SPEAr300 ...
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... SPEAr300 List of figures Figure 1. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. SPEAr300 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. Clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4. Multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 5. Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 6. Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 7. DDR2 Read cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 8. DDR2 Read cycle path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 9. DDR2 Write cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 10. DDR2 Write cycle path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 11 ...
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... Description 1 Description The SPEAr300 is a member of the SPEAr family of embedded MPUs for networked devices based on the powerful ARM926EJ-S processor (up to 333 MHz), widely used in applications where high computation performance is required. In addition, SPEAr300 has an MMU that allows virtual memory management -- making the system compliant with advanced operating systems like Linux ...
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... SPEAr300 1.1 Main features: ● ARM926EJ-S 32-bit RISC CPU 333 MHz – 16 Kbytes of instruction cache, 16 Kbytes of data cache – 3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code density, bytecode Java mode (Jazelle™) for direct execution of Java code. ...
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... JTAG IEEE 1149.1 ● Boundary scan ● ETM functionality multiplexed on primary pins ● Supply voltages – 1.2 V core, 1.8 V/2.5 V DDR, 2.5 V PLLs, 1.5 V RTC and 3.3 V I/Os ● Operating temperature °C ● LFBGA289 (15 x15 mm, pitch 0.8 mm) 10/83 Doc ID 16324 Rev 2 SPEAr300 ...
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... ARM926EJ-S CPU The core of the SPEAr300 is an ARM926EJ-S reduced instruction set computer (RISC) processor. It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of Java byte codes ...
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... DDR_CLK @ 100-333 MHz for DDR memory interface. The above frequencies are the maximum allowed values. The clock frequencies can be modified by programming the clock system registers. The clock system consists of 2 main parts: a multi clock generator block and two internal PLLs. 12/83 Doc ID 16324 Rev 2 SPEAr300 ...
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... MHz or a sub-multiple (/2, /4, /8). 2.2.2 Power saving system mode control Using three mode control bits, the system controller switch the SPEAr300 to any one of four different modes: DOZE, SLEEP, SLOW and NORMAL. ● SLEEP mode: In this mode the system clocks, HCLK and CPU_CLK, are disabled and the System Controller clock is driven by a low speed oscillator (nominally 32768 Hz) ...
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... Each GPT consists of 2 channels, each one made programmable 16-bit counter and a dedicated 8-bit timer clock prescaler. The programmable 8-bit prescaler performs a clock division 256, and different input frequencies can be chosen through SPEAr300 configuration registers (frequencies ranging from 3. MHz can be synthesized). ...
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... Multichannel DMA controller Within its basic subsystem, SPEAr300 provides an DMA controller (DMAC) able to service independent DMA channels for sequential data transfers between single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and peripheral-to-peripheral). ...
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... MB address space each ● SMI clock signal (SMICLK) is generated by SMI (and input to all slaves) ● SMICLK can MHz in fast read mode (or 20 MHz in normal mode). It can be controlled by 7 programmable bits. 16/83 Doc ID 16324 Rev 2 SPEAr300 ...
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... SPEAr300 2.11 Flexible static memory controller (FSMC) SPEAr300 provides a Flexible Static Memory Controller (FSMC) which interfaces the AHB bus to external NAND/NOR Flash memories and to asynchronous SRAM memories. Main features: ● Provides an interface between AHB system bus and external parallel memory devices ● ...
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... CRC algorithm for SIR and MIR, and 32-bit CRC algorithm for FIR. 2.14 Synchronous serial port (SSP) SPEAr300 provides one synchronous serial port (SSP) block that offers a master or slave interface for synchronous serial communication with slave or master peripherals Main features: ● ...
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... SPEAr300 2.15 I2C The I2C controller, acts as an APB slave interface to the two-wire serial I2C bus. Main features: ● Compliance to the I2C-bus specification (Philips) 2 ● v2.0 compatible. ● Operates in three different speed modes: – Standard (100 kbps) – Fast (400 kbps) – ...
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... Timeslot bufferization: data from DIN is stored in an input buffer and data from an output buffer is played on DOUT. When the number of samples stored/played reaches the buffer size, the processor is interrupted in order to read the input buffer and prepare a new output buffer (or a DMA request is generated). 20/ devices=8). Doc ID 16324 Rev 2 SPEAr300 2 C devices at the ...
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... SPEAr300 2 2. interface 2 The I S interface is very similar to the TDM block, but the frame sync is limited to Philips I definition composed of 4 signals: ● I2S_LRCK; Left and right channels synchronization (Master/slave) 2 ● I2S_CLK clock (Master/slave) 2 ● I2S_DIN clock (Master/slave) ● I2S DOUT: I The DOUT line can be high impedance when out of samples. Data is always stored in 32 bit format in the buffer ...
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... Architecture overview 2.20 Keyboard controller SPEAr300 provides a GPIO/keyboard controller block which is a two-mode input and output port. Main features: ● The selection between the two modes is an APB Bus programmable bit. ● Keyboard interface uses 18 pins ● 18-bit general-purpose parallel port with input or output single pin programmability ● ...
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... SPEAr300 2.22 Camera interface The camera interface receives data from a sensor in parallel mode (8 to 14-bits) by storing a full line in a buffer memory, then requesting a DMA transfer or interrupting the processor. When all the lines of a frame are transferred, a frame sync interrupt is generated. Main features: ● ...
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... Designed to work with I/O cards, read-only cards and read/write cards ● Error correction code (ECC) support for MMC4.2 cards ● Supports read wait control, suspend/resume operation ● Supports FIFO overrun and underrun condition by stopping the SD clock ● Conforms to AMBA specification AHB (2.0) 24/83 Doc ID 16324 Rev 2 SPEAr300 ...
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... AHB master bus width, supporting 32, 64, and 128-bit wide data transactions ● It supports both little and big endian memory architectures 2.25 USB2 host controller SPEAr300 has a fully independent USB 2.0 host controller, consisting of the following six major blocks: ● An EHCI block for high-speed transfers (HS mode, 480 Mbps) ● ...
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... A USB plug detect (UPD) which detects the connection of a cable. 2.27 JPEG (CODEC) SPEAr300 provides a JPEG CODEC with header processing (JPGC), able to decode (or encode) image data contained in the RAM memory, from the JPEG (or MCU) format to the MCU (or JPEG) format. Main features: ● ...
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... SPEAr300 2.28 Cryptographic co-processor (C3) Main features: ● Supported cryptographic algorithms: – Advanced encryption standard (AES) cipher in ECB, CBC, CTR modes – Data encryption standard (DES) cipher in ECB and CBC modes. – SHA-1, HMAC-SHA-1, MD5, HMAC-MD5 digests. ● Instruction driven DMA based programmable engine. ...
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... Oversampling min 32, max 256 ● S/N ratio is 82 dB, THD (Measured kHz sine wave x64 over sampled by the processor and x32 by the DAC) ● Dynamic: 80% of full scale ● Optionally, the order of the noise shaper can be set to 1 28/83 Doc ID 16324 Rev 2 SPEAr300 ...
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... SPEAr300 3 Pin description The following tables describe the pinout of the SPEAr300 listed by functional block. List of abbreviations Pull Pull Down 3.1 Required external components 1. DDR_COMP_1V8: place an external 121 kresistor between ball P4 and ball R4 2. USB_TX_RTUNE: connect an external 43.2 k pull-down resistor to ball K5 3. DIGITAL_REXT: place an external 121 k ...
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... J15 BOOT_SEL J14 nTRST L16 Input TDO L15 Output TCK L17 Input TDI L14 Input TMS L13 Input Doc ID 16324 Rev 2 SPEAr300 Ball Value 1.2 V 2.5 V 3.3 V 1.2 V 2.5 V 3.3 V 1.2 V 2.5 V 3.3 V 1.2V 1.2V 2.5 V 2.5 V 2.5 V 1.8 V 2.5 V 1.5 V ...
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... SPEAr300 Table 5. Serial memory interface (SMI) pin description Group SMI_DATAOUT SMI Signal name Ball Direction SMI_DATAIN M13 Input M14 Output SMI_CLK N17 SMI_CS_0 M15 Output SMI_CS_1 M16 Doc ID 16324 Rev 2 Pin description Function Serial Flash input TTL Input Buffer data 3.3 V tolerant, PU ...
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... TTL Input Buffer 3.3 V tolerant, PD Over-current Reference resistor Analog Test Output Function ADC analog input channel Analog buffer 2.5 ADC negative voltage reference ADC positive voltage reference SPEAr300 Pin type Bidirectional tolerant Bidirectional tolerant mA Bidirectional tolerant mA Analog Analog Pin type V tolerant ...
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... SPEAr300 Table 8. DDR pin description Group DDR_ADD_0 DDR_ADD_1 DDR_ADD_2 DDR_ADD_3 DDR_ADD_4 DDR_ADD_5 DDR_ADD_6 DDR_ADD_7 DDR_ADD_8 DDR_ADD_9 DDR_ADD_10 DDR_ADD_11 DDR DDR_ADD_12 DDR_ADD_13 DDR_ADD_14 DDR_CLKEN DDR_CLK_N Signal name Ball Direction Output DDR_BA_0 P7 DDR_BA_1 P8 Output DDR_BA_2 R8 DDR_RAS U8 Output DDR_CAS T8 Output DDR_WE T7 Output U7 Output DDR_CLK_P ...
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... SSTL_2/SSTL_18 Data Lines I/O (Upper byte) Upper Data I/O Strobe SSTL_2/SSTL_18 Upper Data Mask I/O SSTL_2/SSTL_18 Upper Gate Open Reference Voltage Return for Ext. Resistors Ext. Resistor TTL Input Buffer Configuration 3.3 V Tolerant, PU SPEAr300 Pin type Differential Differential Analog Power Analog ...
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... The 98 PL_GPIO and 4 PL_CLK pins have the following characteristics: – Output buffer: TTL 3.3 V capable – Input buffer: TTL, 3.3 V tolerant, selectable internal pull up/pull down (PU/PD) The PL_GPIOs can be configured in 13 different modes. This allows SPEAr300 to be tailored for use in various applications, see 3.3.1 PL_GPIO pin description Table 9. ...
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... CAMu_wLCD Mode (14-bit camera without LCD) ● CAMl_LCD Mode (8-bit camera with LCD) Configuration 1 is the default mode for SPEAr300. It supports the FSMC interface for NAND Flash connectivity and boot pins used for selecting the boot mode. Mode 1: NAND interface NAND mode mainly provides: ● ...
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... SPEAr300 Mode 5: High end IP phone Main features: ● 9x9 keyboard ● CLCD controller interface ● 4 SPI/I2C control signals ● Digital-to-analog converter (DAC) ● TDM block capable of communicating with 2 external devices ● I2S block ● SDIO interface supporting SPI, SD1, SD4 and SD8 mode ● ...
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... Digital-to-analog converter (DAC) ● I2S block ● TDM block capable of communicating with 2 external devices ● SDIO interface supporting SPI, SD1, SD4 and SD8 mode ● GPIOs with interrupt capability 38/83 Doc ID 16324 Rev 2 SPEAr300 ...
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... The second multiplexer is controlled by RAS register 1 and allows you to enable the I/O functions shown in alternate functions column of To get more information about these registers, please refer to the SPEAr300 user manual. and can be enabled/disabled using by via RAS register 1. Figure 4 are controlled by different registers. The first Table 11) ...
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Figure 4. Multiplexing scheme Alternate functions PL_GPIO 16 bits RAS register 2 RAS register 1 RAS IP configuration mode 1 RAS IP configuration mode 13 4 bits ...
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... SPEAr300 Table 10. Available peripherals in each configuration mode 16-bit 1 4 NAND 16-bit 2 4 NOR 16-bit 3 NAND 8-bit 8 8 NOR 8-bit NAND /NOR TDM interfacing using GPIOs In some configuration modes where less than 8 TDM devices are indicated in additional TDM devices can be supported by using GPIO pins. The TDM needs a dedicated interrupt line, an SPI and an independent frame sync signal to interface each device ...
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Table 11. PL_GPIO multiplexing scheme PL_GPIO_# / ball number PL_GPIO_97/H16 /E1 /E1 /E1 PL_GPIO_96/H15 D0 DQ0 D0 PL_GPIO_95/H14 D1 DQ1 D1 PL_GPIO_94/H13 D2 DQ2 D2 PL_GPIO_93/G17 D3 DQ3 D3 PL_GPIO_92/G16 D4 DQ4 D4 PL_GPIO_91/G15 D5 DQ5 D5 ...
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Table 11. PL_GPIO multiplexing scheme (continued) PL_GPIO_# / ball number PL_GPIO_73/A17 0 A7 CLD7 G8_7 (out) PL_GPIO_72/B16 0 A8 CLD8 PL_GPIO_71/D14 0 A9 CLD9 PL_GPIO_70/C15 0 A10 CLD10 PL_GPIO_69/A16 0 A11 CLD11 PL_GPIO_68/B15 0 A12 CLD12 PL_GPIO_67/C14 ...
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Table 11. PL_GPIO multiplexing scheme (continued) PL_GPIO_# / ball number PL_GPIO_51/D10 0 0 CLLP PL_GPIO_50/A12 0 0 CLLE PL_GPIO_49/C11 0 0 CLPP PL_GPIO_48/B11 B0 B0 CLD22 SPI_I2C0 PL_GPIO_47/C10 B1 B1 CLD23 SPI_I2C1 PL_GPIO_46/A11 B2 B2 GPIO7 SPI_I2C2 ...
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Table 11. PL_GPIO multiplexing scheme (continued) PL_GPIO_# / ball number PL_GPIO_30/ SD_DAT1 SD_DAT1 PL_GPIO_29/ SD_DAT2 SD_DAT2 SD_SDAT PL_GPIO_28/ SD_SDAT3 3 SD_SDAT PL_GPIO_27/ SD_SDAT4 4 SD_SDAT PL_GPIO_26/ SD_SDAT5 ...
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Table 11. PL_GPIO multiplexing scheme (continued) PL_GPIO_# / ball number PL_GPIO_8/ SD_WP SD_WP PL_GPIO_7/ PL_GPIO_6/ SD_LED SD_LED PL_GPIO_5/ PL_GPIO_4/ PL_GPIO_3/D1 /E4 /E4 /E4 PL_GPIO_2/E4 ...
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... SPEAr300 Notes/legend for GPIO (General purpose I/O): basGPIO: Base GPIOs in the basic subsystem (enabled as alternate functions) G10 and G8: GPIOs in the RAS subsystem GPIOx: GPIOs in the independent GPIO block in the RAS subsystem TDM_ : TDM interface signals SD_ : SDIO interface IT pins: interrupts Table cells filled with ‘0’ or ‘1’ are unused and unless otherwise configured as Alternate function or GPIO, the corresponding pin is held at low or high level respectively by the internal logic ...
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... BSR Value Functional I/O BSR Value Functional I/O BSR Value Functional I/O BSR Value Functional I/O BSR Value Functional I/O BSR Value Functional I/O Doc ID 16324 Rev 2 SPEAr300 Case 3 - Full Debug 0 1 0/1 0/1 0 nTRST_ARM TCK_ARM TSM_ARM TDI_ARM TDO_ARM ARM_TRACE_CLK ARM_TRACE_PKTA[0] ...
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... SPEAr300 Table 13. Ball sharing during debug (continued) Signal PL_GPIO[73] PL_GPIO[72:0] Case 1 - Board Debug Case 2 - Static Debug BSR Value Functional I/O Doc ID 16324 Rev 2 Pin description Case 3 - Full Debug ARM_TRACE_PKTB[7] 49/83 ...
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... SPI 0xD01F.FFFF I2C 0xD07F.FFFF - 0xD0FF.FFFF JPEG CODEC 0xD17F.FFFF IrDA 0xD1FF.FFFF - Doc ID 16324 Rev 2 SPEAr300 Description Low power DDR or DDR2 Action memory Buffer memory Sync memory I2S memory bank 1 I2S memory bank 2 NAND bank0 NAND bank1 NAND bank2 NAND bank3 NOR bank0 ...
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... SPEAr300 Table 14. Memory mapping (continued) Start address 0xD280.0000 0xD300.0000 0xE0800.0000 0xE100.0000 0xE110.0000 0xE120.0000 0xE130.0000 0xE180.0000 0xE190.0000 0xE1A0.0000 0xE210.0000 0xE220.0000 0xE280.0000 0xE290.0000 0xE800.0000 0xF000.0000 0xF010.0000 0xF110.0000 0xF120.0000 0xF800.0000 0xFC00.0000 0xFC20.0000 0xFC40.0000 0xFC60.0000 0xFC80.0000 0xFC88.0000 0xFC90.0000 0xFC98.0000 0xFCA0.0000 0xFCA8.0000 0xFCB0.0000 0xFCB8.0000 0xFD00.0000 0xFF00.0000 ...
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... Supply voltage for the analog blocks (2) Supply voltage for the I/Os Maximum power consumption Doc ID 16324 Rev 2 Minimum value Maximum value - 0.3 1.44 - 0.3 3 0.3 2.16 -0.3 2.16 -55 150 -40 125 Max 420 160 (3) 930 SPEAr300 Unit °C °C Unit mA mA µ ...
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... SPEAr300 3. The maximum current and power values listed above, obtained with typical supply voltages, are not guaranteed to be the highest obtainable. These values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages ...
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... ADC. Min Max = 3V3 29 103 DDE Min Max -0.3 V -0.15 REF -0.3 V -0.125 REF V +0.15 V 2V5+0.3 REF DDE V +0.125 V 1V8+0.3 REF DDE 200 Min Typ 40.5 45 44.1 49 SPEAr300 Unit Unit V V Unit k k Unit Max Unit 49.5 53.9 ...
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... SPEAr300 Table 24. On die termination Symbol Termination value of resistance for on die RT1* Termination value of resistance for on die RT2* Table 25. Reference voltage Symbol V REFIN 5.7 Power up sequence It is recommended to power up the power supplies in the order shown in brought up first, followed by Figure 5. Power-up sequence V 1 ...
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... The MRESET must remain active for at least 10 ms after all the power supplies are in the correct range and should become active in no more than 10 µs when one of the power supplies goes out of the correct range. 56/83 Power-down sequence Doc ID 16324 Rev 2 SPEAr300 ...
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... SPEAr300 6 Timing requirements 6.1 DDR2 timing characteristics The characterization timing is done considering an output load all the DDR pads. The operating conditions are in worst case V=1. 40° 6.1.1 DDR2 read cycle timings Figure 7. DDR2 Read cycle waveforms DQS DQ Figure 8. DDR2 Read cycle path ...
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... Figure 10. DDR2 Write cycle path Table 27. DDR2 Write cycle timings Frequency 333 MHz 266 MHz 200 MHz 166 MHz 133 MHz 58/83 t4 max 2. max 1.36 1.55 1.86 2.11 2.49 Doc ID 16324 Rev 2 SPEAr300 t5 max 260 ps 634 max Unit -1.55 ns -1.36 ns -1. 794 ns -420 ns ...
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... SPEAr300 6.1.3 DDR2 command timings Figure 11. DDR2 Command waveforms CLK ADDRESS, STROBEs, AND CONTROL LINES Figure 12. DDR2 Command path Table 28. DDR2 Command timings Frequency 333 MHz 266 MHz 200 MHz 166 MHz 133 MHz 6.2 CLCD timing characteristics The characterization timing is done considering an output load all the outputs.The operating conditions are in worst case V=0.90 V T=125 ° ...
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... Tclock Tmax Tmin Tstabl SET Q CLR t3 Value ) 6 ns CLOCK ) 0. 0. -0.04 ns 3.62 ns 2.34 ns direct max - ( max min + [t direct max - (t max CLOCK Doc ID 16324 Rev 2 Tf CLD[23:0],CLAC,CLLE, CLLP,CLFP ,CLPOWER t2 CLCP Frequency 166 MHz + t )]/2} = 4.7915 ns max min SPEAr300 Tr the min ...
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... SPEAr300 6.2.2 CLCD timing characteristics divided clock Figure 15. CLCD waveform with CLCP divided CLCP CLD[23:0],CLAC,CLLE,CLLP, CLFP ,CLPOWER Figure 16. CLCD block diagram with CLCP divided CLCDCLK Table 105. Table 30. CLCD timings with CLCP divided Parameter t divided max CLOCK t divided max rise (t ...
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... Those values are referred to the common internal source clock which has a period of ns. HCLK 62/83 =125° worst case and V =1. signals Min 8.1067 SCLH 7.9874 SCLL 7.5274 SDAH 7.4081 SDAL Doc ID 16324 Rev 2 Set D Q Clr Q Set D Q Clr Q Max 11.8184 12.6269 11.2453 12.0530 SPEAr300 = 40° SCL SDA Unit ...
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... SPEAr300 Figure 19. Output signal waveforms for I The timing of high and low level of SCL (t Table 32. Time characteristics for I Table 33. Time characteristics for I Table 34. Time characteristics for signals SCLHigh high-speed mode Parameter t SU-STA t HD-STA t SU-DAT t HD-DAT t SU-STO t HD-STO fast speed mode Parameter t SU-STA ...
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... I C controller of SPEAr300 is one-clock cycle based (6 ns with the HCLK clock at 166 MHz). This time may be insufficient for some slave devices. A few slave devices may not receive the valid address due to the lack of SDA hold time and will not acknowledge even if the address is valid ...
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... SPEAr300 6.4.1 8-bit NAND Flash configuration Figure 21. Output pads for 8-bit NAND Flash configuration HCLK Figure 22. Input pads for 8-bit NAND Flash configuration NFRB NFIO_0..7 CLPOWER CLLP CLLE CLFP CLCP CLAC CLD_23..22 Figure 23. Output command signal waveforms for 8-bit NAND Flash configuration ...
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... TIO (h=1) Note: Values in Table 35 THCLK = 6 ns. 66/83 T ALE Address Data Out READ -> IO NFIO -> FFs Min -16.85 ns -16.84 ns 11.10 ns 11.18 ns 3.43 ns are referred to the common internal source clock which has a period of Doc ID 16324 Rev 2 SPEAr300 Max -19.38 ns -19.37 ns 13.04 ns 13.05 ns 8.86 ns ...
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... SPEAr300 6.4.2 16-bit NAND Flash configuration Figure 26. Output pads for 16-bit NAND Flash configuration HCLK Figure 27. Input pads for 16-bit NAND Flash configuration NFRB NFIO_0..7 CLPOWER CLLP CLLE CLFP CLCP CLAC CLD_23..22 Figure 28. Output command signal waveforms 16-bit NAND Flash configuration ...
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... TIO (h=1) Note: Values in Table 36 THCLK = 6 ns. 68/83 T ALE Address Data Out READ -> IO NFIO -> FFs Min -16.85 ns -16.84 ns 11.10 ns 11.18 ns 3.27 ns are referred to the common internal source clock which has a period of Doc ID 16324 Rev 2 SPEAr300 Max -19.38 ns -19.37 ns 13.04 ns 13.05 ns 11.35 ns ...
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... SPEAr300 6.5 Ether MAC 10/100 Mbps timing characteristics The characterization timing is given for an output load the MII TX clock and the other pads. The operating conditions are in worst case V=0.90 V T=125° C and in best case V=1. 40° C. 6.5.1 MII transmit timing specifications Figure 31 ...
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... Figure 33. MII RX waveforms MII_RXCLK MII_RXD0-MII_RXD3, MII_RXER, MII_RXDV Figure 34. Block diagram of MII RX pins MII_RX[0..3], MII_RXER, MII_RXDV MII_RXCLK 6.5.3 MDIO timing specifications Figure 35. MDC waveforms MDC Input MDIO Output 70/83 Tclock Tclock Tsetup Thold Tmax Tmi n Doc ID 16324 Rev 2 SPEAr300 SET Q Q CLR Tf Tr ...
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... SPEAr300 Figure 36. Paths from MDC/MDIO pads INPUT CLK Table 38. MDC/MDIO timing Parameter t period CLK t fall (t ) CLK f t rise (t ) CLK max CLK min CLK SETUPmax max HOLDmin min Note: When MDIO is used as output the data are launched on the falling edge of the clock as ...
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... SMIDATAIN timings Signal SMI_DATAIN Figure 38. SMIDATAOUT/SMICSn data paths OUTPUT SMICLK 72/ input_delay D SMI_DATAIN SMI_CLK_i t CD SMI_CLK t SMIDATAIN arrival Parameter t d_max t d_min t cd_min t cd_max t SETUP_max t HOLD_min Doc ID 16324 Rev Value SMIDATAIN_arrival_max input_delay SMIDATAIN_arrival_min input_delay t SMI_CLK_i_arrival_min t SMI_CLK_i_arrival_max d_max cd_min d_min cd_max HCLK HCLK SPEAr300 HCLK ...
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... SPEAr300 Figure 39. SMIDATAOUT timings SMI_CLK SMIDATAOUT(FAST) SMIDATAOUT(SLOW) Table 40. SMIDATAIN timings Signal SMI_DATAOUT Figure 40. SMICSn fall timings Table 41. SMICSn fall timings Signal SMI_CSn fall t t delay_min delay_max Parameter t t delay_max arrivalSMIDATAOUT_max t t delay_min arrivalSMIDATAOUT_min Parameter t t delay_max arrivalSMICSn_max_fall t t delay_min arrivalSMICSn_min_fall Doc ID 16324 Rev 2 ...
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... Input setup-hold/output delay Max Fall time 1.82 Rise time 1.63 Input setup time 8.27 Input hold time -2.59 2.03 fall 1.92 rise 1.69 fall 1.78 rise 1.63 Doc ID 16324 Rev 2 SPEAr300 Value - t arrival_SMI_CLK_min_fall - t arrival_SMI_CLK_max_fall Min Unit 1.40 1.19 ns ...
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... SPEAr300 6.7 SSP timing characteristics This module provides a programmable length shift register which allows serial communication with other SSP devices through wire interface (SSP_CLK, SSP_MISO, SSP_MOSI and SSP_CSn). The SSP supports the following features: ● Master/Slave mode operations ● Chip-selects for interfacing to multiple slave SPI devices. ...
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... SSP_CLK (output) rising or falling edge Delay time, SSP_CLK (output) rising or falling edge to SSP_CSn (output) rising edge Doc ID 16324 Rev 2 Min Max -0.411 -0.342 -0.411 -0.342 0.912 1.720 0.912 1.720 Min Max Clock -3.138 2.175 Clock -3.138 2.175 T/2 T SPEAr300 Unit Unit ...
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... SPEAr300 Figure 43. SPI master mode external timing (clock phase = 0) 6.7.2 SPI master mode timings (clock phase = 1) Table 47. Timing requirements for SPI master mode (clock phase = 1) No. t su(DIV- 4 CLKL) t su(DIV- 5 CLKH) t h(CLKL- 6 DIV) t h(CLKH- 7 DIV) Table 48. Switching characteristics over recommended operating conditions for SPI master mode (clock phase = ...
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... Figure 45. UART transmit and receive timings 78/83 Parameters Delay time, SSP_CSn (output) falling edge to first SSP_CLK (output) rising or falling edge Delay time, SSP_CLK (output) rising or falling edge to SSP_CSn (output) rising edge (Input) (Output) Doc ID 16324 Rev 2 SPEAr300 Min Max Unit T ns T/2 ns ...
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... SPEAr300 Table 49. UART transmit timing characteristics S.No Table 50. UART receive timing characteristics S.No where ( UART baud rate Parameters UART Maximum Baud Rate UART Pulse Duration Transmit Data (TxD) UART Transmit Start Bit Parameters UART Pulse Duration Receive Data (RxD) UART Receive Start Bit ...
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... Doc ID 16324 Rev 2 SPEAr300 inches Min. Typ. Max. 0.0669 0.0106 0.0387 0.0078 0.0315 0.0177 0.0197 0.0217 0.5846 0.5906 0.5965 0.5039 0.5846 0.5906 0.5965 ...
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... SPEAr300 Figure 46. LFBGA289 package dimensions Table 52. Thermal resistance characteristics Package LFBGA289 °C/W) JC 18.5 Doc ID 16324 Rev 2 Package information °C/W) JB 24.5 81/83 ...
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... Updated Section 5: Electrical timing characteristics, Section 6.4: FSMC timing characteristics timing characteristics Added Table 52: Thermal resistance characteristics information. Doc ID 16324 Rev 2 Changes Section 2: Architecture overview Table 10 on page 41 characteristics, Section 6.1: DDR2 2 Section 6. timing characteristics, and Section 6.7: SSP in Package SPEAr300 ...
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... SPEAr300 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...