SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet - Page 15

• Manufacturer Part Number: SPEAR300-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR300-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr300
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 56 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10849-5

SPEAr300
2.6
2.7
2.8
2.9
2.10
RTC oscillator
The RTC provides a 1-second resolution clock. This keeps time when the system is inactive
and can be used to wake the system up when a programmed alarm time is reached. It has a
clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a
secured time update.
Multichannel DMA controller
Within its basic subsystem, SPEAr300 provides an DMA controller (DMAC) able to service
up to 8 independent DMA channels for sequential data transfers between single source and
destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and
peripheral-to-peripheral).
Each DMA channel can support a unidirectional transfer, with internal four-word FIFO per
channel.
Embedded memory units
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The size of available SRAM varies according to the peripheral configuration mode See
Table
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Mobile DDR/DDR2 memory controller
SPEAr300 integrates a high performances multi-channel memory controller able to support
low power Mobile DDR and DDR2 double data rate memory devices. The multi-port
architecture ensures memory is shared efficiently among different high-bandwidth client
modules.
It has 6 internal ports. One of them is reserved for register access during the controller
initialization while the other five are used to access the external memory.
It also include the physical layer (PHY) and some DLLs that allow fine tuning of all the timing
parameters to maximize the data valid windows at any frequency in the allowed range.
Serial memory interface
SPEAr300 provides a serial memory interface (SMI) to SPI-compatible off-chip memories.
These serial memories can be used for both data storage and code execution.
32 Kbytes of BootROM
Up to 57 Kbytes of SRAM
57 Kbytes in modes 1 and 2
8 Kbytes in modes 3 to 13.
10.:
Doc ID 16324 Rev 2
Architecture overview
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