SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet - Page 18

IC MPU ARM9 289LFBGA

SPEAR300-2

Manufacturer Part Number
SPEAR300-2
Description
IC MPU ARM9 289LFBGA
Manufacturer
STMicroelectronics
Series
SPEAr®r
Datasheet

Specifications of SPEAR300-2

Processor Type
ARM Microprocessor
Speed
333MHz
Voltage
1.14 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
289-LFBGA
Processor Series
SPEAr300
Core
ARM926EJ-S
Data Bus Width
16 bit
Maximum Clock Frequency
333 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Data Ram Size
56 KB
Interface Type
I2C, UART, USB, Serial
Number Of Programmable I/os
62
Number Of Timers
6
Program Memory Size
32 KB
Program Memory Type
ROM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-10849-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SPEAR300-2
Manufacturer:
ST
Quantity:
12 005
Part Number:
SPEAR300-2
Manufacturer:
ST
0
Part Number:
SPEAR300-2
Manufacturer:
ST
Quantity:
20 000
Architecture overview
2.14
18/83
Main features:
Synchronous serial port (SSP)
SPEAr300 provides one synchronous serial port (SSP) block that offers a master or slave
interface for synchronous serial communication with slave or master peripherals
Main features:
Supports IrDA serial infrared physical layer specification (IrPHY), version 1.3
Supports IrDA link access protocol (IrLAP), version 1.1
Serial infrared (SIR), with rates 9.6 Kbps, 19.2 Kbps, 38.4 Kbps, 57.6 Kbps and
115.2 Kbps
Medium infrared (MIR), with rates 576 Kbps and 1.152 Mbps
Fast infrared (FIR), with rate 4 Mbps.
Transceiver interface compliant with all IrDA transceivers with configurable TX and RX
signal polarity.
Half-duplex infrared frame transmission and reception.
16-bit CRC algorithm for SIR and MIR, and 32-bit CRC algorithm for FIR.
Maximum speed of 41.5 Mbps
Master and slave mode capability
Programmable clock bit rate and prescale
Separate transmit and receive first-in, first-out memory buffers, 16 bits wide, 8 locations
deep
Programmable choice of interface operation:
Programmable data frame size from 4 to 16-bit.
Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts
DMA interface
SPI (Motorola)
Microwire (National Semiconductor)
TI synchronous serial
Doc ID 16324 Rev 2
SPEAr300

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