SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet - Page 42

• Manufacturer Part Number: SPEAR300-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR300-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr300
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 56 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10849-5

Table 11.
PL_GPIO_97/H16
PL_GPIO_96/H15
PL_GPIO_95/H14
PL_GPIO_94/H13
PL_GPIO_93/G17
PL_GPIO_92/G16
PL_GPIO_91/G15
PL_GPIO_90/G14
PL_GPIO_89/F17
PL_GPIO_88/F16
PL_GPIO_87/G13
PL_GPIO_86/E17
PL_GPIO_85/F15
PL_GPIO_84/D17
PL_GPIO_83/E16
PL_GPIO_82/E15
PL_GPIO_81/C17
PL_GPIO_80/D16
PL_GPIO_79/F14
PL_GPIO_78/D15
PL_GPIO_77/B17
PL_GPIO_76/F13
PL_GPIO_75/E14
PL_GPIO_74/C16
PL_GPIO_# /
ball number
PL_GPIO multiplexing scheme
D10
D11
D12
D13
D14
D15
/E1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
1
0
0
0
0
0
0
0
DQ15 A-1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
/E1
A0
A1
A2
A3
A4
A5
A6
2
CLD0
CLD1
CLD2
CLD3
CLD4
CLD5
CLD6
D10
D11
D12
D13
D14
D15
/E1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
3
G8_0 (out)
G8_1 (out)
G8_2 (out)
G8_3 (out)
G8_6 (out)
G8_4(out)
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
G8_5
(out)
4
1
Configuration mode (enabled by RAS register 2)
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
CLD0
CLD1
CLD2
CLD3
CLD4
CLD5
CLD6
5
1
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
6
1
0
0
0
0
0
0
0
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
CLD0
CLD1
CLD2
CLD3
CLD4
CLD5
CLD6
7
1
G8_0
G8_1
G8_2
G8_3
G8_4
G8_5
G8_6
G8_7
/E1
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
8
G8_0
G8_1
G8_2
G8_3
G8_4
G8_5
G8_6
G8_7
/E1
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
10
1
DIO0_1
DIO1_1
DIO2_1
DIO3_1
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
COL0
COL1
COL2
COL3
COL4
CLD0
CLD1
CLD2
CLD3
CLD4
CLD5
CLD6
11
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DIO0_1
DIO1_1
DIO2_1
DIO3_1
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
COL0
COL1
COL2
COL3
COL4
12
1
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
CLD0
CLD1
CLD2
CLD3
CLD4
CLD5
CLD6
13
1
register 1)
Alternate
(enabled
function
by RAS