SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet - Page 11

• Manufacturer Part Number: SPEAR300-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR300-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr300
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 56 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10849-5

SPEAr300
2
2.1
Architecture overview
The SPEAr300 internal architecture is based on several shared subsystem logic blocks
interconnected through a multilayer interconnection matrix.
The switch matrix structure allows different subsystem dataflow to be executed in parallel
improving the core platform efficiency.
High performance master agents are directly interconnected with the memory controller
reducing the memory access latency. The overall memory bandwidth assigned to each
master port can be programmed and optimized through an internal efficient weighted round-
robin arbitration mechanism.
Figure 2.
ARM926EJ-S CPU
The core of the SPEAr300 is an ARM926EJ-S reduced instruction set computer (RISC)
processor.
It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off
between high performance and high code density and includes features for efficient
execution of Java byte codes.
The ARM CPU and is clocked at a frequency up to 333 MHz. It has a 16-Kbyte instruction
cache, a 16-Kbyte data cache, and features a memory management unit (MMU) which
makes it fully compliant with Linux and WindowsCE operating systems.
It also includes an embedded trace module (ETM Medium+) for real-time CPU activity
tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed
trace mode, with normal or half-rate clock.
NAND Flash
NAND Flash
Mobile DDR
Mobile DDR
Mobile DDR
Mobile DDR
D b
D b
Debug, trace
Debug, trace
NOR Flash
NOR Flash
EEPROM
EEPROM
SRAM
SRAM
Flash
Flash
DDR2
DDR2
SD-Card
SD-Card
MMC
MMC
SDIO
SDIO
t
t
Note: Some interfaces share I/Os. Not all interfaces shown in the figure can be used
Note: Some interfaces share I/Os. Not all interfaces shown in the figure can be used
concurrently
SPEAr300 overview
FSMC
SDIO/MMC
ETM9
JTAG
controller
controller
memory
controller
SMI
DDR
Keypad
24 MHz
GPIO
Clock, reset
RTC
32 kHz
TouchScreen
Doc ID 16324 Rev 2
up to 333 MHz
8-channel DMA
3 Timers / WD
ARM 926EJ
JPEG Codec
accelerator
accelerator
C3 Crypto
ADC
interface
Camera
SPEAr300
SPEAr300
LCD controller
Standard OS
support
Interrupt/syst controller
57 KB embed. SRAM
32 KB embed. ROM
MMU
CODEC/SLICs
External
Phy
TDM
USB2.0 PHY
USB2.0 PHY
USB2.0 PHY
USB2.0 PHY
USB2.0 PHY
USB2.0 PHY
IdDA
Internet
access
I2C
I2C
I2S
Architecture overview
CODECs
Audio
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