SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet - Page 35

• Manufacturer Part Number: SPEAR300-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR300-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr300
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 56 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10849-5

SPEAr300
3.3
3.3.1
3.3.2
Shared I/O pins (PL_GPIOs)
SPEAr300 devices feature, in the Reconfigurable Array Subsystem (RAS), specific sets of
IPs as well as groups of software controllable GPIOs (that can be used alternatively). In the
SPEAr300 the following IPs are implemented in the RAS:
●
●
●
●
●
●
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The 98 PL_GPIO and 4 PL_CLK pins have the following characteristics:
The PL_GPIOs can be configured in 13 different modes. This allows SPEAr300 to be
tailored for use in various applications, see
PL_GPIO pin description
Table 9.
Configuration modes
This section describes the main operating modes created by using a selection of the
embedded IPs.
13 configurations are available selected by RAS register 2. The peripherals available in each
configuration are shown in
Details of each PL_GPIO pin are given for each mode in
scheme.
PL_GPIOs
Group
FSMC NAND/NOR Flash interface
GPIO/Keyboard controller
8-bit camera interface
CLCD controller interface
Digital-to-analog converter (DAC)
I2S
4 SPI/I2C control signals
TDM block
SDIO interface
GPIOs
–
–
Output buffer: TTL 3.3 V capable up to 10 mA
Input buffer: TTL, 3.3 V tolerant, selectable internal pull up/pull down (PU/PD)
PL_GPIO pin description
PL_GPIO_97...
PL_GPIO_0
PL_CLK1...
PL_CLK4
Signal name
Table 10: Available peripherals in each configuration mode
Doc ID 16324 Rev 2
(see
Table
Ball
11)
Section
Direction
I/O
3.3.2.
Table 11: PL_GPIO multiplexing
General
purpose I/O or
multiplexed pins
(see
Programmable
logic external
clocks
Function
Table
11)
Pin description
introduction of
the
above)
(see the
Pin type
Section 3.3
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