SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet - Page 25

• Manufacturer Part Number: SPEAR300-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR300-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr300
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 56 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10849-5

SPEAr300
2.24
Note:
2.25
Ethernet controller
SPEAr300 provides an Ethernet MAC 10/100 Universal (commonly referred to as GMAC-
UNIV), enabling to transmit and receive data over Ethernet in compliance with the IEEE
802.3-2002 standard.
GMAC is a hardware block implementing Ethernet MAC layer 2 processing. GMAC is
configured for 10/100 Mbps operation on SPEAr3xx family and up to 1 Gbps on SPEAr600.
Main features:
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USB2 host controller
SPEAr300 has a fully independent USB 2.0 host controller, consisting of the following six
major blocks:
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This host can manage an external power switch, providing a control line to enable or disable
the power, and an input line to sense any over-current condition detected by the external
switch.
The Host controller is capable of managing two different devices at a time on its two
downstream ports.
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Compliant with the IEEE 802.3-2002 standard
Supports the default MII interface to the external PHY
Supports 10/100 Mbps data transfer rates
Local FIFO available (4 Kbyte RX, 2 Kbyte TX)
Supports both half-duplex and full-duplex operation. In half-duplex operation,
CSMA/CD protocol is provided for, as well as packet bursting and frame extension at
100 Mbps
Programmable frame length to support both standard and jumbo Ethernet frames with
size up to 16 Kbyte
A variety of flexible addresses filtering modes are supported
A set of control and status registers (CSRs) to control MAC core operation
Native DMA with single-channel transmit and receive engines
DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining
An AHB slave acting as programming interface to access all CSRs, for both DMA and
MAC core subsystems
An AHB master for data transfer to system memory
32-bit AHB master bus width, supporting 32, 64, and 128-bit wide data transactions
It supports both little and big endian memory architectures
An EHCI block for high-speed transfers (HS mode, 480 Mbps)
2 OHCI blocks for full and low speed transfers (FS and LS modes, 12 and 1.5 Mbps)
Local 2-Kbyte FIFO
Local DMA
Integrated USB2 transceiver (PHY)
An HS device connected to either of the two ports is managed by the EHCI.
An FS/LS device connected to port0 is managed by OHCI0.
An FS/LS device connected to port1 is managed by OHCI1.
Doc ID 16324 Rev 2
Architecture overview
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