AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 98

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 52. Programmable Delays (DLYBCS, DLYBS and DLYBCT)
Clock Generation
In master mode, the SPI master clock is either MCKI or
MCKI/32, as defined by the MCK32 field of SP_MR. The
SPI baud rate clock is generated by dividing the SPI master
clock by a value between 4 and 510. The divisor is defined
in the SCBR field in each chip select register. The transfer
speed can thus be defined independently for each chip
select signal.
CPOL and NCPHA in the chip select registers define the
clock/data relationship between master and slave devices.
CPOL defines the inactive value of the SPCK. NCPHA
defines which edge causes data to change and which edge
causes data to be captured.
In slave mode, the input clock low and high pulse duration
must strictly be longer than two system clock (MCKI) peri-
ods.
Peripheral Data Controller
The SPI is closely connected to two Peripheral Data Con-
troller channels. One is dedicated to the receiver. The other
is dedicated to the transmitter.
98
SPCK Output
Chip Select 2
Chip Select 1
AT91M63200
Change peripheral
DLYBCS
DLYBS
of peripheral
No change
The PDC channel is programmed using SP_TPR (Transmit
Pointer) and SP_TCR (Transmit Counter) for the transmit-
ter and SP_RPR (Receive Pointer) and SP_RCR (Receive
Counter) for the receiver. The status of the PDC is given in
SP_SR by the SPENDTX bit for the transmitter and by the
SPENDRX bit for the receiver.
The pointer registers (SP_TPR and SP_RPR) are used to
store the address of the transmit or receive buffers. The
counter registers (SP_TCR and SP_RCR) are used to
store the size of these buffers.
The receiver data transfer is triggered by the RDRF bit and
the transmitter data transfer is triggered by TDRE. When a
transfer is performed, the counter is decremented and the
pointer is incremented. When the counter reaches 0, the
status bit is set (SPENDRX for the receiver, SPENDTX for
the transmitter in SP_SR) and can be programmed to gen-
erate an interrupt. While the counter is at zero, the status
bit is asserted and transfers are disabled.
DLYBCT
DLYBCT