AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 86

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

USART Channel Status Register
Name:
Access Type:
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86
RXRDY: Receiver Ready
0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled.
1 = At least one complete character has been received and the US_RHR has not yet been read.
TXRDY: Transmitter Ready
0 = US_THR contains a character waiting to be transferred to the Transmit Shift Register, or an STTBRK command has
been requested.
1 = US_THR is empty and there is no break request pending TSR availability.
Equal to zero when the USART is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one.
RXBRK: Break Received/End of Break
0 = No Break Received nor End of Break detected since the last “Reset Status Bits” command in the Control Register.
1 = Break Received or End of Break detected since the last “Reset Status Bits” command in the Control Register.
ENDRX: End of Receive Transfer
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
ENDTX: End of Transmit Transfer
0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.
1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
OVRE: Overrun Error
0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the
last “Reset Status Bits” command.
1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted
since the last “Reset Status Bits” command.
FRAME: Framing Error
0 = No stop bit has been detected low since the last “Reset Status Bits” command.
1 = At least one stop bit has been detected low since the last “Reset Status Bits” command.
PARE: Parity Error
1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last “Reset Status
Bits” command.
0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last “Reset Status Bits” com-
mand.
TIMEOUT: Receiver Time-out
0 = There has not been a time-out since the last “Start Time-out” command or the Time-out Register is 0.
1 = There has been a time-out since the last “Start Time-out” command.
TXEMPTY: Transmitter Empty
0 = There are characters in either US_THR or the Transmit Shift Register or a break is being transmitted.
1 = There are no characters in US_THR and the Transmit Shift Register and break is not active.
Equal to zero when the USART is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one.
COMMTX: ARM7TDMI ICE Debug Communication Channel Transmit Status
For USART0 only. Refer to the ARM7TDMI datasheet for a complete description of this flag.
COMMRX: ARM7TDMI ICE Debug Communication Channel Receive Status
For USART0 only. Refer to the ARM7TDMI datasheet for a complete description of this flag.
COMMRX
PARE
31
23
15
–
–
7
COMMTX
FRAME
AT91M63200
30
22
14
US_CSR
Read only
–
–
6
OVRE
29
21
13
–
–
–
5
ENDTX
28
20
12
–
–
–
4
ENDRX
27
19
11
–
–
–
3
RXBRK
26
18
10
–
–
–
2
TXEMPTY
TXRDY
25
17
–
–
9
1
TIMEOUT
RXRDY
24
16
–
–
8
0