AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet

IC ARM7 MCU 176 TQFP

AT91M63200-25AI

Manufacturer Part Number
AT91M63200-25AI
Description
IC ARM7 MCU 176 TQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91M63200-25AI

Core Processor
ARM7
Core Size
16/32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, WDT
Number Of I /o
58
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
176-TQFP, 176-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91M63200-25AI
Manufacturer:
Atmel
Quantity:
10 000
Errata Sheet V1.0
This Errata Sheet refers to:
6. Warning: Additional NWAIT Constraints
AT91M63200-25AI
The following datasheets:
AT91M63200 Summary, Rev. 1028DS–05/00
AT91M63200, Rev. 1028A–10/99
AT91M43300 Summary, Rev. 1322A–10/99
AT91M43300, AT91M63200 Electrical Characteristics, Rev. 1090B–05/00
176-lead TQFP and 144-ball BGA devices with the following markings:
When the NWAIT signal is asserted during an external memory access, the fol-
lowing EBI behavior is correct:
In these cases, the access is delayed as required by NWAIT and the access oper-
ations are correctly performed.
In other cases, the following erroneous behavior occurs:
At maximum speed, asserting the NWAIT in the first access cycle is not possible,
as the sum of the timings “MCKI Falling to Chip Select” and “NWAIT setup to
MCKI rising” are generally higher than one half of a clock period. This leads to
using at least one standard wait state. However, this is not sufficient except to per-
form byte or half-word read accesses. Word and write accesses require at least
two standard wait states.
NWAIT is asserted before the first rising edge of the master clock and
respects the NWAIT to MCKI rising setup timing as defined in the Electrical
Characteristics datasheet.
NWAIT is sampled inactive and at least one standard wait state remains to
be executed, even if NWAIT does not meet the NWAIT to first MCKI rising
setup timing (i.e., NWAIT is asserted only on the second rising edge of
MCKI).
32-bit read accesses are not managed correctly and the first 16-bit data
sampling takes into account only the standard wait states. 16- and 8-bit
accesses are not affected.
During write accesses of any type, the NWE rises on the rising edge of the
last cycle as defined by the programmed number of wait states. However,
NWAIT assertion does affect the length of the total access. Only the NWE
pulse length is inaccurate.
Internal Product
Reference 55560A
AT91M43300-25CI
AT91
ARM
Microcontrollers
AT91M63200
AT91M43300
Errata Sheet
V1.0
®
Thumb
Rev. 1781B–01/02
®
1

Related parts for AT91M63200-25AI

AT91M63200-25AI Summary of contents

Page 1

... AT91M43300 Summary, Rev. 1322A–10/99 AT91M43300, AT91M63200 Electrical Characteristics, Rev. 1090B–05/00 • 176-lead TQFP and 144-ball BGA devices with the following markings: AT91M63200-25AI Internal Product Reference 55560A 6. Warning: Additional NWAIT Constraints When the NWAIT signal is asserted during an external memory access, the fol- lowing EBI behavior is correct: – ...

Page 2

... MCKI must be met. Figure 2. Number of Standard Wait States is Two MCKI NWAIT (1) 1 NCS Standard Access Length with Two Wait States Note: 1. These numbers refer to the standard access cycles. AT91M63200/AT91M43300 Errata Sheet 2 EB16 (1) 2 (1) 3 1781B–01/02 ...

Page 3

... NWAIT assertion. However, the NWE signal waveform is unchanged, and rises too early. Figure 4. Description of the Number of Standard Wait States MCKI NWAIT NWE NCS Access Length = One Wait State + Assertion of the NWAIT for One More Cycle 1781B–01/02 AT91M63200/AT91M43300 Errata Sheet First Data Sampling (Erroneous) 2 (1) 2 (1) 1 (1) EB16 Second Data ...

Page 4

... AT91M63200 Datasheet – Page 99 Problem Fix/Workaround The reset value of the Status Register does not need to be defined at zero. The status of the SPI is updated at each cycle after the reset and the SPENDRX and SPENDTX bits are set, because the PDC counters are 0. ...

Page 5

... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical ® ...

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