AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 13

IC ARM7 MCU 176 TQFP

AT91M63200-25AI

Manufacturer Part Number
AT91M63200-25AI
Description
IC ARM7 MCU 176 TQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91M63200-25AI

Core Processor
ARM7
Core Size
16/32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, WDT
Number Of I /o
58
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
176-TQFP, 176-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91M63200-25AI
Manufacturer:
Atmel
Quantity:
10 000
Data Bus Width
A data bus width of 8 or 16 bits can be selected for each
chip select. This option is controlled by the DBW field in the
EBI_CSR (Chip Select Register) for the corresponding chip
select.
Figure 8 shows how to connect a 512K x 8-bit memory on
NCS2.
Figure 8. Memory Connection for an 8-bit Data Bus
Figure 9 shows how to connect a 512K x 16-bit memory on
NCS2.
Figure 9. Memory Connection for a 16-bit Data Bus
EBI
EBI
D8 - D15
A1 - A19
D8 - D15
A1 - A18
D0 - D7
D0 - D7
NWR1
NWR0
NCS2
NCS2
NWE
NOE
NUB
NRD
NLB
A0
D0 - D7
D8 - D15
A0 - A18
Low Byte Enable
High Byte Enable
Write Enable
Output Enable
Memory Enable
D0 - D7
A1 - A18
A0
Write Enable
Output Enable
Memory Enable
Byte Write or Byte Select Access
Each chip select with a 16-bit data bus can operate with
one of two different types of write access:
This option is controlled by the BAT field in the EBI_CSR
(Chip Select Register) for the corresponding chip select.
Byte Write access is used to connect 2 x 8-bit devices as a
16-bit memory page.
Figure 10 shows how to connect two 512K x 8-bit devices
in parallel on NCS2.
Figure 10. Memory Connection for 2 x 8-bit Data Buses
Byte Write access supports two byte-write and a single
read signal.
Byte Select access selects upper and/or lower byte with
two byte-select lines, and separate read and write
signals.
The signal A0/NLB is not used.
The signal NWR1/NUB is used as NWR1 and enables
upper byte writes.
The signal NWR0/NWE is used as NWR0 and enables
lower byte writes.
The signal NRD/NOE is used as NRD and enables half-
word and byte reads.
EBI
D8 - D15
A1 - A19
D0 - D7
NWR1
NWR0
NCS2
NRD
A0
AT91M63200
D0 - D7
A0 - A18
Write Enable
Read Enable
Memory Enable
D8 - D15
A0 - A18
Write Enable
Read Enable
Memory Enable
13

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