AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet
AT91M63200-25AI
Specifications of AT91M63200-25AI
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AT91M63200-25AI Summary of contents
Page 1
... Available in a 176-lead TQFP Package Description The AT91M63200 is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications ...
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... Pin Configuration Table 1. AT91M63200 Pinout Pin AT91M63200 1 GND 2 GND 3 NCS0 4 NCS1 5 NCS2 6 NCS3 7 NLB/ VDDIO 16 GND A10 20 A11 21 A12 22 A13 23 A14 24 A15 25 A16 26 A17 27 A18 28 A19 29 VDDIO 30 GND 31 A20/CS7 32 A21/CS6 33 A22/CS5 34 A23/CS4 VDDCORE 44 VDDIO AT91M63200 2 Pin AT91M63200 Pin 45 GND 89 46 GND ...
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... Pin Description Table 2. AT91M63200 Pin Description Module Name Function A0 - A23 Address Bus D0 - D15 Data Bus CS4 - CS7 Chip Select NCS0 - NCS3 Chip Select NWR0 Lower Byte 0 Write Signal NWR1 Lower Byte 1 Write Signal EBI NRD Read Signal NWE Write Enable NOE ...
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... Table 2. AT91M63200 Pin Description (Continued) Module Name Function JTAGSEL Selects between JTAG and ICE Mode TMS Test Mode Select JTAG/ICE TDI Test Data In TDO Test Data Out TCK Test Clock NTRST Test Reset Input VDDIO I/O Power Power VDDCORE Core Power ...
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... Block Diagram Figure 2. AT91M63200 JTAGSEL NTRST TMS TDO TDI TCK MCKI PB17/MCKO PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PA9/IRQ0 PA10/IRQ1 P PA11/IRQ2 Interrupt Controller PA12/IRQ3 I PA13/FIQ O PA14/SCK0 PA15/TXD0 PA16/RXD0 PA17/SCK1 PA18/TXD1/NTRI PA19/RXD1 PA20/SCK2 PA21/TXD2 ...
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... Electrical and Mechanical Charac- teristics” (Literature No. 1090). The ARM standard In-Circuit Emulation debug interface is supported via the ICE port of the AT91M63200 via the JTAG/ICE port when JTAGSEL is low. IEEE JTAG bound- ary scan is supported via the JTAG/ICE port when JTAG- SEL is high ...
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... Memory Map Figure 3. AT91M63200 Memory Map Fixed Internal Area Programmable Base Address and Page Size Fixed Internal Area On-chip Peripherals External Memory [7] External Memory [6] External Memory [5] External Memory [4] External Memory [3] External Memory [2] External Memory [1] External Memory [0] MPI On-chip RAM (during BOOT) ...
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... Peripheral Memory Map Figure 4. AT91M63200 Peripheral Memory Map 3M bytes AT91M63200 8 AIC: Advanced Interrupt Controller Reserved WD: Watchdog Timer PMC: Power Management Controller PIO: Parallel I/O Controller B PIO: Parallel I/O Controller A Reserved TC: Timer/Counter Channels TC: Timer/Counter Channels Reserved USART 2 USART 1 USART 0 SPI Reserved SF: Special Function ...
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... Except for the program counter, the ARM core registers do not have defined reset states. When reset is active, the inputs of the AT91M63200 must be held at valid logic levels. The EBI address lines drive low during reset. All the peripheral clocks are disabled during reset to save power (see " ...
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... The EBI user interface is described on page 31. Figure 5. External Memory Smaller than Page Size Memory Map AT91M63200 10 External Memory Mapping The memory map associates the internal 32-bit address space with the external 24-bit address bus. The memory map is defined by programming the base address and page size of the external memories (see EBI user interface registers EBI_CSR0 to EBI_CSR7) ...
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... Write enable (output) Upper and lower byte select (output) Wait request (input) Functions Allows from chip select lines to be used 16-bit data bus Byte-write or byte-select access Byte-write or byte-select access Byte-write or byte-select access AT91M63200 Type Output I/O Output Output Output Output Output ...
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... EBI NWRx A0 - A19 D0 - D15 Note: For eight external devices, the maximum address space per device is 1M byte. AT91M63200 12 The selection is controlled by the ALE field in EBI_MCR (Memory Control Register). The following combinations are possible: A20, A21, A22, A23 (configuration by default) A20, A21, A22, CS4 ...
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... Figure 10. Memory Connection for 2 x 8-bit Data Buses D15 D8 - D15 A1 - A19 A0 - A18 EBI A0 Low Byte Enable NWR1 High Byte Enable NWR0 Write Enable NRD Output Enable NCS2 Memory Enable AT91M63200 A18 Write Enable Read Enable Memory Enable D8 - D15 A0 - A18 Write Enable Read Enable Memory Enable 13 ...
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... However necessary to boot from nonvolatile memory at page zero. When the AT91M63200 is reset, the memory map is modi- fied to place NVM at page zero. The on-chip RAM is remapped to address 0x00300000 and either on-chip 32-bit NVM or off-chip 8/16-bit NVM is remapped to address 0x00000000 ...
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... No wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type or between external and internal memory accesses. Early read wait states affect the external bus only. They do not affect internal bus timing. AT91M63200 Figure 13. Standard Read Protocol MCKI ADDR NCS ...
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... Data output In early read protocol the data can remain valid longer than in standard read protocol due to the additional wait cycle which follows a write access. AT91M63200 16 Wait States The EBI can automatically insert wait states. The different types of wait states are listed below: Standard wait states • ...
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... When NWAIT is de-asserted, the EBI finishes the access sequence. Figure 19. External Wait MCKI ADDR NWAIT NCS NWE NRD (1) Notes: 1. Early read protocol 2. Standard read protocol t The NWAIT signal must meet setup and hold requirements DF on the rising edge of the clock. AT91M63200 (2) 17 ...
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... A chip select wait state is automatically inserted when con- secutive accesses are made to two different external mem- ories (if no wait states have already been inserted). If any wait states have already been inserted (e.g. data float wait), then none are added. AT91M63200 18 Figure 20. Chip Select Wait mem 1 chip select wait ...
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... Memory Access Waveforms Figures 21 through 24 show examples of the two alternative protocols for external memory read access. Figure 21. Standard Read Protocol with AT91M63200 19 ...
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MCKI A0-A23 NRD NWE NCS 1 NCS 2 D0-D15 (Mem 1) D0-D15 (AT91) D0-D15 (Mem 2) read read write early read mem 1 mem 2 mem 2 wait cycle chip ...
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MCKI A0-A23 NRD NWE NCS 1 NCS D0-D15 (Mem 1) D0-D15 (AT91) D0-D15 (Mem 2) read mem 2 read mem 1 read mem 2 data data float wait ...
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MCKI A0-A23 NRD NWE NCS 1 NCS D0-D15 (Mem 1) D0-D15 (AT91) D0-D15 (Mem 2) early read read wait mem 2 read mem 1 read mem 2 data ...
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... Figures 25 through 31 show the timing cycles and wait states for read and write access to the various AT91M63200 exter- nal memory devices. The configurations described are as follows: Table 4. Memory Access Waveforms Figure Number Number of Wait States Bus Width AT91M63200 Size of Data Transfer ...
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... Figure 25. 0 Wait States, 16-bit Bus Width, Word Transfer MCKI A1-A23 NCS NLB NUB READ ACCESS • Standard Protocol NRD D0-D15 Internal Bus • Early Protocol NRD D0-D15 WRITE ACCESS • Byte Write/ Byte Select Option NWE D0-D15 AT91M63200 24 ADDR ADDR ...
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... Figure 26. 1 Wait State, 16-bit Bus Width, Word Transfer MCKI A1-A23 NCS NLB NUB Read Access • Standard Protocol NRD D0-D15 Internal Bus • Early Protocol NRD D0-D15 Write Access • Byte Write/ Byte Select Option NWE D0-D15 1 wait state ADDR AT91M63200 1 wait state ADDR ...
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... Figure 27. 1 Wait State, 16-bit Bus Width, Half-word Transfer MCKI A1-A23 NCS READ ACCESS • Standard Protocol D0-D15 Internal Bus • Early Protocol NRD D0-D15 WRITE ACCESS • Byte Write/ Byte Select Option NWE D0-D15 AT91M63200 26 1 wait state NLB NUB NRD ...
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... Figure 28. 0 Wait States, 8-bit Bus Width, Word Transfer MCKI ADDR A0-A23 NCS READ ACCESS • Standard Protocol NRD D0-D15 Internal Bus • Early Protocol NRD D0-D15 WRITE ACCESS NWR0 NWR1 D0-D15 ADDR+1 ADDR AT91M63200 ADDR ...
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... Figure 29. 1 Wait State, 8-bit Bus Width, Half-word Transfer 1 wait state MCKI A0-A23 NCS READ ACCESS • Standard Protocol NRD D0-D15 Internal Bus • Early Protocol NRD D0-D15 WRITE ACCESS NWR0 NWR1 D0-D15 AT91M63200 28 1 wait state ADDR ADDR ...
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... Figure 30. 1 Wait State, 8-bit Bus Width, Byte Transfer MCKI A0-A23 NCS READ ACCESS • Standard Protocol NRD D0-D15 Internal Bus • Early Protocol NRD D0-D15 WRITE ACCESS NWR0 NWR1 D0-D15 1 wait state AT91M63200 ...
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... Figure 31. 0 Wait States, 16-bit Bus Width, Byte Transfer MCKI A1-A23 Internal Address NCS NLB NUB READ ACCESS • Standard Protocol NRD D0-D15 Internal Bus • Early Protocol NRD D0-D15 WRITE ACCESS • Byte Write Option NWR0 NWR1 D0-D15 • Byte Select Option NWE AT91M63200 30 ADDR ADDR ADDR ADDR ...
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... Memory Control Register Notes: 1. 8-bit boot (if BMS is detected high) 2. 16-bit boot (if BMS is detected low) AT91M63200 Eight chip select registers (EBI_CSR0 to EBI_CSR7) are used to program the parameters for the individual external memories. Each EBI_CSR must be programmed with a dif- ferent base address, even for unused chip selects. ...
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... NWS: Number of Wait States This field is valid only if WSE is set. NWS Number of Standard Wait States • WSE: Wait State Enable 0 = Wait state generation is disabled. No wait states are inserted Wait state generation is enabled. AT91M63200 – CSEN BAT WSE NWS – – – TDF PAGES DBW ...
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... CSEN: Chip Select Enable 0 = Chip select is disabled Chip select is enabled. • BA: Base Address These bits contain the highest bits of the base address. If the page size is larger than 1M byte, the unused bits of the base address are ignored by the EBI decoder AT91M63200 33 ...
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... A20, A21, A22 A20, A21 A20 none • DRP: Data Read Protocol 0 = Standard read protocol for all external memory devices enabled Early read protocol for all external memory devices enabled. AT91M63200 – – – – – – – – – ...
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... MPI: Multi-processor Interface The AT91M63200 family features a second bus interface which is dedicated to parallel data transfers with an exter- nal processing device. The MPI is based byte Dual-port RAM (DPRAM) and an arbiter. Both the ARM core and the external processor can read and write to any location in the DPRAM ...
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... Note AT91M63200 36 Function Active high bus request input Active high bus grant output Active low chip select input Active high read and active low write input Active low output enable Active low lower byte select Active low upper byte select 9-bit address bus ...
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... M63X00 External MPI Processor PIO Output MPI_BR PIO Input MPI_BG Address Bus MPI_A1 - MPI_A9 Data Bus MPI_D0 - MPI_D15 MPI_NCS R/W MPI_RNW PB0/MPI_NOE PB1/MPI_NLB PB2/MPI_NUB AT91M63200 AT91 Microcontroller EBI PIO Output PIO Input Address Bus Data Bus NCSx NWE/NWR0 NOE/NRD A0/NLB NUB/NWR1 37 ...
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... AT91 in case it needs to access the MPI reduce the time during which it is stopped. After having performed these actions, the external proces- sor must inform the AT91M63200 that data has been read or written. This may be done by positioning an external interrupt signal NIRQ0-NIRQ3 or NFIQ flagging. In ...
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... AIC: Advanced Interrupt Controller The AT91M63200 has an 8-level priority, individually- maskable, vectored interrupt controller. This feature sub- stantially reduces the software and real-time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast inter- rupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor’ ...
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... AT91M63200 40 Interrupt Description FIQ Fast interrupt SWIRQ Soft interrupt (generated by the AIC) US0IRQ USART Channel 0 interrupt US1IRQ USART Channel 1 interrupt US2IRQ USART Channel 2 interrupt SPIRQ SPI interrupt TC0IRQ Timer Channel 0 interrupt TC1IRQ Timer Channel 1 interrupt TC2IRQ Timer Channel 2 interrupt TC3IRQ Timer Channel 3 interrupt ...
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... Hence, at the end of a higher priority interrupt, the AIC returns to the previous state corresponding to the pre- ceding lower priority interrupt which had been interrupted. AT91M63200 Interrupt Handling The interrupt handler must read the AIC_IVR as soon as possible. This de-asserts the NIRQ request to the proces- sor and clears the interrupt in case it is programmed to be edge triggered ...
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... In either case, an End-of-Interrupt command would be nec- essary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system. Hence, the debug system would become AT91M63200 42 strongly intrusive, and could cause the application to enter an undesired state. This is avoided by using Protect Mode. ...
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... Interrupt Set Command Register 0x130 End of Interrupt Command Register 0x134 Spurious Vector Register Note: 1. The reset value of this register depends on the level of the external IRQ lines. All other sources are cleared at reset. AT91M63200 Name Access AIC_SMR0 Read/Write AIC_SMR1 Read/Write – ...
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... Program the input to be positive- or negative-edge triggered or positive- or negative-level sensitive. The active level or edge is not programmable for the internal sources. SRCTYPE Internal Sources 0 0 Level Sensitive 0 1 Edge Triggered 1 0 Level Sensitive 1 1 Edge Triggered AT91M63200 – – – – – – – ...
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... AIC Source Vector Register Register Name: AIC_SVR0...AIC_SVR31 Access Type: Read/Write Reset Value • VECTOR: Interrupt Handler Address The user may store in these registers the addresses of the corresponding handler for each interrupt source VECTOR VECTOR VECTOR VECTOR AT91M63200 ...
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... AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Read only Reset Value • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0 which corre- sponds to FIQ. AT91M63200 IRQV IRQV IRQV IRQV 29 ...
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... AIC Interrupt Status Register Register Name: AIC_ISR Access Type: Read only Reset Value --- --- 23 22 --- --- 15 14 --- --- 7 6 --- --- • IRQID: Current IRQ Identifier The Interrupt Status Register returns the current interrupt source number --- --- --- --- --- --- --- --- --- --- AT91M63200 --- --- --- --- --- --- --- --- --- IRQID 47 ...
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... Corresponding interrupt is pending. AIC Interrupt Mask Register Register Name: AIC_IMR Access Type: Read only Reset Value IRQ0 IRQ1 23 22 --- --- 15 14 --- PIOBIRQ 7 6 TC1IRQ TC0IRQ • Interrupt Mask 0 = Corresponding interrupt is disabled Corresponding interrupt is enabled. AT91M63200 IRQ2 IRQ3 --- --- --- --- PIOAIRQ WDIRQ TC5IRQ SPIRQ US2IRQ US1IRQ 29 28 ...
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... AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read only Reset Value --- --- 23 22 --- --- 15 14 --- --- 7 6 --- --- • NFIQ: NFIQ Status 0 = NFIQ line inactive NFIQ line active. • NIRQ: NIRQ Status 0 = NIRQ line inactive NIRQ line active --- --- --- --- --- --- --- --- --- --- --- --- AT91M63200 --- --- --- --- --- --- --- --- --- --- NIRQ NFIQ 49 ...
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... No effect Enables corresponding interrupt. AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: Write only 31 30 IRQ0 IRQ1 23 22 --- --- 15 14 --- PIOBIRQ 7 6 TC1IRQ TC0IRQ • Interrupt Disable effect Disables corresponding interrupt. AT91M63200 IRQ2 IRQ3 --- --- --- --- PIOAIRQ WDIRQ TC5IRQ SPIRQ US2IRQ US1IRQ 29 ...
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... PIOBIRQ 7 6 TC1IRQ TC0IRQ • Interrupt Set effect Sets corresponding interrupt IRQ2 IRQ3 --- --- --- --- PIOAIRQ WDIRQ TC5IRQ SPIRQ US2IRQ US1IRQ IRQ2 IRQ3 --- --- --- --- PIOAIRQ WDIRQ TC5IRQ SPIRQ US2IRQ US1IRQ AT91M63200 --- --- --- --- --- --- TC4IRQ TC3IRQ TC2IRQ US0IRQ SWIRQ FIQ --- --- --- --- --- --- TC4IRQ TC3IRQ TC2IRQ US0IRQ SWIRQ FIQ 51 ...
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... AIC Spurious Vector Register Register Name: AIC_SPU Access Type: Read/Write Reset Value • SPUVEC: Spurious Interrupt Vector Handler Address The user may store the address of the spurious interrupt handler in this register. AT91M63200 – – – – – – – – ...
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... SPSR (SPSR_irq). Note that the Link Register must be decremented by 4 when it is saved restored directly into the Program Counter at the end of the interrupt. AT91M63200 5. Further interrupts can then be unmasked by clear- ing the I-bit in the CPSR, allowing re-assertion of the NIRQ to be taken into account by the core. This can occur if an interrupt with a higher priority than the current one occurs ...
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... In this case only, it de-asserts the NFIQ line on the processor. 4. The previous step has the effect of branching to the corresponding interrupt service routine not AT91M63200 54 necessary to save the Link Register (r14_fiq) and the SPSR (SPSR_fiq) if nested fast interrupts are not needed ...
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... PIO: Parallel I/O Controller The AT91M63200 has 58 programmable I/O lines. 14 pins on the AT91M63200 are dedicated as general-purpose I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins (see Tables 9 and 10). These lines are controlled by two separate and identical PIO Controllers called PIOA and PIOB ...
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... Figure 38. Parallel I/O Multiplexed with a Bi-directional Signal Pad Output Enable Pad Output Pad Pad Input AT91M63200 PIO_PSR PIO_MDSR Filter 1 0 PIO_IFSR PIO_PSR PIO_PDSR Event Detection PIO_ISR PIO_IMR PIO_OSR 1 Peripheral 0 Output Enable PIO_ODSR 1 Peripheral 0 Output 0 Peripheral Input 1 PIOIRQ ...
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... SPI Master In Slave Out SPI Master Out Slave In SPI Peripheral Chip Select 0 SPI Peripheral Chip Select 1 SPI Peripheral Chip Select 2 SPI Peripheral Chip Select 3 – – – – AT91M63200 Signal Direction Reset State Input PIO Input Bi-directional PIO Input Bi-directional PIO Input Input ...
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... TIOB2 28 – 29 – 30 – 31 – Note: 1. Bit number refers to the data bit which corresponds to this signal in each of the User Interface registers AT91M63200 58 Peripheral Signal Description MPI Output Enable MPI Lower Byte Select MPI Upper Byte Select – – – – – ...
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... The reset value of this register depends on the level of the external pins at reset. 2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have occurred on any pins between the reset and the read. AT91M63200 Name Access ...
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... P15 P14 This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral func- tion is enabled on the corresponding pin Disables PIO control (enables peripheral control) on the corresponding pin effect. AT91M63200 P29 P28 P27 P21 P20 ...
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... This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or dis- abled PIO is active on the corresponding line (peripheral is inactive PIO is inactive on the corresponding line (peripheral is active P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M63200 P26 P25 P24 P18 P17 P16 P10 ...
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... P15 P14 This register is used to disable PIO output drivers. If the pin is driven by the peripheral, this has no effect on the pin, but the information is stored. The register is programmed as follows Disables the PIO output on the corresponding pin effect. AT91M63200 P29 P28 P27 P21 ...
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... PIO. The register reads as follows The corresponding PIO is output on this line The corresponding PIO is input on this line P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M63200 P26 P25 P24 P18 P17 P16 P10 ...
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... P23 P22 15 14 P15 P14 This register is used to disable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is pro- grammed as follows Disables the glitch filter on the corresponding pin effect. AT91M63200 P29 P28 P27 P21 P20 P19 13 12 ...
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... This register indicates which pins have glitch filters selected updated when PIO outputs are enabled or disabled by writing to PIO_IFER or PIO_IFDR Filter is selected on the corresponding input (peripheral and PIO Filter is not selected on the corresponding input P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M63200 P26 P25 P24 P18 P17 P16 P10 ...
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... P14 This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored PIO output data on the corresponding pin is cleared effect. AT91M63200 P29 P28 P27 21 20 ...
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... The corresponding pin is at logic The corresponding pin is at logic P29 P28 P27 P21 P20 P19 P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M63200 P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 P18 P17 P16 P10 ...
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... P23 P22 15 14 P15 P14 This register is used to disable PIO interrupts on the corresponding pin. It has an effect whether the PIO is enabled or not Disables the interrupt on the corresponding pin. Logic level changes are still detected effect. AT91M63200 P29 P28 P27 P21 P20 P19 ...
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... No input change has been detected on the corresponding pin since the register was last read P29 P28 P27 P21 P20 P19 P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M63200 P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 P18 P17 P16 P10 ...
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... Access Type: Write only 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to disable the open drain configuration of the output buffer Disables the multi-driver option on the corresponding pin effect. AT91M63200 P29 P28 P27 P21 P20 P19 P13 P12 P11 5 ...
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... P15 P14 This register indicates which pins are configured with open drain drivers PIO is configured as an open drain PIO is not configured as an open drain P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91M63200 P26 P25 P24 P18 P17 P16 P10 ...
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... USART: Universal Synchronous/Asynchronous Receiver/Transmitter The AT91M63200 provides three identical, full-duplex, uni- versal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Periph- eral Data Controller. The main features are: Programmable baud rate generator • Parity, framing and overrun error detection • ...
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... Baud Rate In synchronous mode with external clock selected (USCLKS[1] = 1), the clock is provided directly by the sig- nal on the SCK pin. No division is active. The value written in US_BRGR has no effect CLK 16-bit Counter OUT > SYNC USCLKS [1] AT91M63200 Selected Clock = CD SYNC 0 Divide Baud Rate Clock 73 ...
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... Example: 8-bit, parity enabled 1 stop 0.5-bit periods RXD Sampling True Start Detection AT91M63200 74 ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver sam- ples the RXD at the theoretical mid-point of each bit assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the sampling point is 8 cycles (0 ...
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... When the counter reaches 0, the TIMEOUT bit in US_CSR is set. The user can restart the wait for a first character with the STTTO (Start Time-out) bit in US_CR. Calculation of time-out duration AT91M63200 × × Duration = Value 4 Bit Period D6 D7 Stop Bit Parity Bit ...
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... Example: 8-bit, parity enabled 1 stop Baud Rate Clock TXD Start Bit AT91M63200 76 (Transmitter Time-guard). When this register is set to zero, no time-guard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte dur- ing the number of bit periods programmed in US_TTGR. Idle state duration ...
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... The standard break transmission sequence is: 1. Wait for the transmitter ready (US_CSR.TXRDY = 1). 2. Send the STTBRK command (write 0x0200 to US_CR). AT91M63200 3. Wait for the transmitter ready (bit TXRDY = 1 in US_CSR). 4. Send the STPBRK command (write 0x0400 to US_CR). The next byte can then be sent: 5 ...
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... The RXD pin level has no effect and the TXD pin is held high idle state. Remote loopback mode directly connects the RXD pin to the TXD pin. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit re-transmis- sion. AT91M63200 78 Figure 45. Channel Modes Automatic Echo Receiver Disabled ...
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... Receiver Time-out Register 0x28 Transmitter Time-guard Register 0x2C Reserved 0x30 Receive Pointer Register 0x34 Receive Counter Register 0x38 Transmit Pointer Register 0x3C Transmit Counter Register AT91M63200 Name Access US_CR Write only US_MR Read/write US_IER Write only US_IDR Write only US_IMR Read only ...
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... STTTO: Start Time-out effect Start waiting for a character before clocking the time-out counter. • SENDA: Send Address effect multi-drop mode only, the next character written to the US_THR is sent with the address bit set. AT91M63200 – – – 21 ...
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... PAR: Parity Type PAR Parity Type Even parity Odd parity Parity forced to 0 (space Parity forced to 1 (mark parity Multi-drop mode – – – – – – NBSTOP USCLKS – AT91M63200 – – – CLKO MODE9 – PAR SYNC – – – 81 ...
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... MODE9: 9-bit Character Length 0 = CHRL defines character length 9-bit character length. • CKLO: Clock Output Select 0 = The USART does not drive the SCK pin The USART drives the SCK pin if USCLKS[ AT91M63200 82 Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved ...
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... COMMRX: Enable ARM7TDMI ICE Debug Communication Channel Receive Interrupt This bit is implemented for USART0 only effect Enables COMMRX Interrupt – – – – – – – – – OVRE ENDTX ENDRX AT91M63200 – – – – – – – TXEMPTY TIMEOUT RXBRK TXRDY RXRDY 83 ...
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... COMMTX: Disable ARM7TDMI ICE Debug Communication Channel Transmit Interrupt This bit is implemented for USART0 only effect Disables COMMTX Interrupt. • COMMRX: Disable ARM7TDMI ICE Debug Communication Channel Receive Interrupt This bit is implemented for USART0 only effect Disables COMMRX Interrupt. AT91M63200 – – – 21 ...
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... COMMRX: ARM7TDMI ICE Debug Communication Channel Receive Interrupt Mask This bit is implemented for USART0 only COMMRX Interrupt is disabled COMMRX Interrupt is enabled – – – – – – – – – OVRE ENDTX ENDRX AT91M63200 – – – – – – – TXEMPTY TIMEOUT RXBRK TXRDY RXRDY 85 ...
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... COMMTX: ARM7TDMI ICE Debug Communication Channel Transmit Status For USART0 only. Refer to the ARM7TDMI datasheet for a complete description of this flag. • COMMRX: ARM7TDMI ICE Debug Communication Channel Receive Status For USART0 only. Refer to the ARM7TDMI datasheet for a complete description of this flag. AT91M63200 – ...
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... RXCHR – – – – – – – – – TXCHR AT91M63200 – – – – – – – – RXCHR – – – – – – – – TXCHR ...
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... Baud Rate (asynchronous mode) = Selected clock / ( 65535 Baud Rate (synchronous mode) = Selected clock / CD Note: In synchronous mode, the value programmed must be even to ensure a 50:50 mark:space ratio. Note: Clock divisor bypass ( must not be used when internal clock MCKI is selected (USCLKS = 0). AT91M63200 – ...
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... Time-guard duration = TG x Bit period – – – – – – – – – – – – – – – – – – AT91M63200 – – – – – – – – – – – – – – – – – – ...
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... Access Type: Read/Write 31 30 – – – – • RXCTR: Receive Counter RXCTR must be loaded with the size of the receive buffer. 0: Stop peripheral data transfer dedicated to the receiver. 1-65535: Start peripheral data transfer if RXRDY is active. AT91M63200 RXPTR RXPTR RXPTR RXPTR – ...
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... TXCTR must be loaded with the size of the transmit buffer. 0: Stop peripheral data transfer dedicated to the transmitter. 1-65535: Start peripheral data transfer if TXRDY is active TXPTR TXPTR TXPTR TXPTR – – – – – – TXCTR TXCTR AT91M63200 – – – – – – ...
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... SPI: Serial Peripheral Interface The AT91M63200 includes an SPI which provides commu- nication with external devices in master or slave mode. Pin Description Seven pins are associated with the SPI interface. When not needed for the SPI function, each of these pins can be con- figured as a PIO. ...
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... SP_MR (Mode Register). The peripheral is defined by the PCS field, also in SP_MR. This option is only available when the SPI is programmed in master mode. AT91M63200 Variable Peripheral Select Variable Peripheral Select is activated by setting bit PS to one. The PCS field in SP_TDR (Transmit Data Register) is used to select the destination peripheral ...
Page 94
... TDRE 0 PS Variable peripheral 1 NPCS = SP_TDR(PCS) Delay DLYBS Serializer = SP_TDR(TD) TDRE = 1 Data Transfer SP_RDR(RD) = Serializer RDRF = 1 Delay DLYBCT TDRE 1 NPCS = 0xF Delay DLYBCS AT91M63200 Fixed peripheral NPCS = SP_MR(PCS Variable peripheral SP_TDR(PCS) New peripheral NPCS = 0xF Delay DLYBCS NPCS = SP_TDR(PCS) 0 Fixed peripheral ...
Page 95
... Figure 48. SPI in Master Mode SP_MR(MCK32) MCKI 0 SPI Master MCKI/32 1 Clock SPIDIS SPIEN MISO SP_MR(PS SP_MR(PCS) SPCK Clock Generator SP_CSRx[15: SP_RDR PCS RD LSB MSB Serializer SP_TDR PCS TD SP_MR(MSTR) AT91M63200 SPCK MOSI NPCS3 NPCS2 NPCS1 NPCS0 SP_SR SP_IER SP_IDR SP_IMR SPIRQ 95 ...
Page 96
... Figure 49. SPI in Slave Mode SCK NSS SPIDIS SPIEN S R MOSI AT91M63200 mode , CPO L, N CPHA and BITS fiel ds of SP_CSR0 are used to define the transfer characteristics. The other chip select registers are not used in slave mode. Q SP_RDR RD LSB ...
Page 97
... MISO MSB (from slave) NSS (to slave) Figure 51. SPI Transfer Format (NCPHA Equals Zero, 8 Bits per Transfer) SPCK cycle (for reference) 1 SPCK (CPOL=0) SPCK (CPOL=1) MOSI (from master) MSB MISO MSB (from slave) X NSS (to slave AT91M63200 LSB 2 1 LSB LSB 2 1 LSB 97 ...
Page 98
... Peripheral Data Controller The SPI is closely connected to two Peripheral Data Con- troller channels. One is dedicated to the receiver. The other is dedicated to the transmitter. AT91M63200 98 No change of peripheral DLYBS DLYBCS The PDC channel is programmed using SP_TPR (Transmit ...
Page 99
... Transmit Pointer Register 0x2C Transmit Counter Register 0x30 Chip Select Register 0 0x34 Chip Select Register 1 0x38 Chip Select Register 2 0x3C Chip Select Register 3 AT91M63200 Name Access SP_CR Write only SP_MR Read/Write SP_RDR Read only SP_TDR Write only SP_SR Read only ...
Page 100
... If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. • SWRST: SPI Software reset effect Resets the SPI. A software-triggered hardware reset of the SPI interface is performed. AT91M63200 100 – – ...
Page 101
... If DLYBCS is less than or equal to six, six SPI master clock periods will be inserted by default. Otherwise, the following equation determines the delay: Delay_ Between_Chip_Selects = DLYBCS * SPI_Master_Clock_period DLYBCS – – – – – – – MCK32 AT91M63200 PCS – – – PCSDEC PS MSTR 101 ...
Page 102
... This field is only used if Variable Peripheral Select is active ( and if the SPI is in master mode. If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS AT91M63200 102 – – – – – ...
Page 103
... The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active. • SPIENS: SPI Enable Status 0 = SPI is disabled SPI is enabled – – – – – – – – – SPENDRX OVRES AT91M63200 – – – – – SPIENS – – – MODF TDRE RDRF 103 ...
Page 104
... OVRES: Overrun Error Interrupt Enable effect Enables the Overrun Error Interrupt. • SPENDRX: End of Receiver Transfer Interrupt Enable effect Enables the End of Receiver Transfer Interrupt. • SPENDTX: End of Transmitter Transfer Interrupt Enable effect Enables the End of Transmitter Transfer Interrupt. AT91M63200 104 – – – – ...
Page 105
... Disables the End of Receiver Transfer Interrupt. • SPENDTX: End of Transmitter Transfer Interrupt Disable effect Disables the End of Transmitter Transfer Interrupt – – – – – – – – – SPENDRX OVRES AT91M63200 – – – – – – – – – MODF TDRE RDRF 105 ...
Page 106
... Overrun Error Interrupt is enabled. • SPENDRX: End of Receiver Transfer Interrupt Mask 0 = End of Receiver Transfer Interrupt is disabled End of Receiver Transfer Interrupt is enabled. • SPENDTX: End of Transmitter Transfer Interrupt Mask 0 = End of Transmitter Transfer Interrupt is disabled End of Transmitter Transfer Interrupt is enabled. AT91M63200 106 – – – 21 ...
Page 107
... RXCTR must be loaded with the size of the receive buffer. 0: Stop peripheral data transfer dedicated to the receiver. 1-65535: Start peripheral data transfer if RDRF is active RXPTR RXPTR RXPTR RXPTR – – – – – – RXCTR RXCTR AT91M63200 – – – – – – 107 ...
Page 108
... Access Type: Read/Write 31 30 – – – – • TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer. 0: Stop peripheral data transfer dedicated to the transmitter. 1-65535: Start peripheral data transfer if TDRE is active. AT91M63200 108 TXPTR TXPTR TXPTR TXPTR 29 ...
Page 109
... The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS[3:0] Bits per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved DLYBCT DLYBS SCBR – AT91M63200 – NCPHA CPOL 109 ...
Page 110
... The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, a delay of four SPI master clock periods are inserted. Otherwise, the following equation determines the delay: Delay_After_Transfer = 32 * DLYBCT * SPI_Master_Clock_period AT91M63200 110 2 x SCBR ...
Page 111
... TC: Timer/Counter The AT91M63200 features two Timer/Counter blocks, each containing three identical 16-bit Timer/Counter channels. Each channel can be independently programmed to per- form a wide range of functions including frequency mea- surement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each Timer/Counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals which can be configured by the user ...
Page 112
... Note: After a hardware reset, the TC clock is disabled by default (see “PMC: Power Management Controller” on page 139). The user must configure the Power Manage- ment Controller before any access to the user interface of the TC. AT91M63200 112 Description External clock inputs Capture mode: general-purpose input ...
Page 113
... The selected clock can be inverted with the CLKI bit in TC_CMR (Channel Mode). This allows counting on the opposite edges of the clock. AT91M63200 The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). ...
Page 114
... Figure 55. Clock Control Selected Trigger Clock CLKSTA Counter Clock AT91M63200 114 Timer/Counter Operating Modes Each Timer/Counter channel can independently operate in two different modes: Capture mode allows measurement on signals • Waveform mode allows wave generation • The Timer/Counter mode is programmed with the WAVE bit in the TC Mode Register ...
Page 115
... Bit ABETRG in TC_CMR selects input signal TIOA or TIOB as an external trigger. Parameter ETRGEDG defines the edge (rising, falling or both) detected to generate an exter- nal trigger. If ETRGEDG = 0 (none), the external trigger is disabled. AT91M63200 Status Register The following bits in the status register are significant in capture operating mode. CPCS: RC Compare Status • ...
Page 116
TCCLKS MCKI/2 MCKI/8 MCKI/32 MCKI/128 MCKI/1024 XC0 XC1 XC2 BURST 1 SWTRG SYNC ABETRG ETRGEDG MTIOB Edge Detector TIOB MTIOA not loaded loaded TIOA Timer/Counter Channel CLKSTA CLKI Capture Register ...
Page 117
... The following events control TIOA and TIOB: software trig- ger, external event and RC Compare. RA Compare con- trols TIOA and RB Compare controls TIOB. Each of these AT91M63200 events can be programmed to set, clear or toggle the out- put as defined in the corresponding parameter in TC_CMR. The tables below show which parameter in TC_CMR is used to define the effect of each event ...
Page 118
TCCLKS MCKI/2 CLKI MCKI/8 MCKI/32 MCKI/128 MCKI/1024 XC0 XC1 XC2 BURST 1 CLK SWTRG SYNC Trig EEVT EEVTEDG ENETRG Edge Detector TIOB Timer/Counter Channel CLKSTA CLKEN CLKDIS Q S CPCDIS CPCSTOP Register A Register B Register ...
Page 119
... Register B 0x1C Register C 0x20 Status Register 0x24 Interrupt Enable Register 0x28 Interrupt Disable Register 0x2C Interrupt Mask Register Note: 1. Read only if WAVE = 0 AT91M63200 Name Access See Table 15 See Table 15 See Table 15 TC_BCR Write only TC_BMR Read/Write Name Access TC_CCR Write only ...
Page 120
... Access Type: Write only 31 30 – – – – – – – – • SYNC: Synchro Command effect Asserts the SYNC signal, which generates a software trigger simultaneously for each of the channels. AT91M63200 120 – – – – – – – – – – ...
Page 121
... TC2XC2S: External Clock Signal 2 Selection TC2XC2S Signal Connected to XC2 0 0 TCLK2 0 1 none 1 0 TIOA0 1 1 TIOA1 – – – – – – – – – TC2XC2S AT91M63200 26 25 – – – – – – TC1XC1S TC0XC0S 24 – 16 – 8 – 0 121 ...
Page 122
... CLKEN: Counter Clock Enable Command effect Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command effect Disables the clock. • SWTRG: Software Trigger Command effect software trigger is performed: the counter is reset and clock is started. AT91M63200 122 – – – – ...
Page 123
... LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs Counter clock is disabled when RB loading occurs – – – – – – – – BURST CLKI AT91M63200 26 25 – – LDRB LDRA 10 9 ABETRG ETRGEDG 2 1 TCCLKS 24 – 123 ...
Page 124
... LDRA: RA Loading Selection LDRA Edge 0 0 none 0 1 rising edge of TIOA 1 0 falling edge of TIOA 1 1 each edge of TIOA • LDRB: RB Loading Selection LDRB Edge 0 0 none 0 1 rising edge of TIOA 1 0 falling edge of TIOA 1 1 each edge of TIOA AT91M63200 124 ...
Page 125
... Counter clock is stopped when counter reaches RC. • CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC Counter clock is disabled when counter reaches RC BEEVT AEEVT – ENETRG BURST CLKI AT91M63200 26 25 BCPC BCPB 18 17 ACPC ACPA 10 9 EEVT EEVTEDG 2 1 TCCLKS 125 ...
Page 126
... ACPC: RC Compare Effect on TIOA ACPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle AT91M63200 126 (1) ...
Page 127
... BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle AT91M63200 127 ...
Page 128
... CV: Counter Value CV contains the counter value in real time. TC Register A Register Name: TC_RA Access Type: Read only if WAVE = 0, Read/Write if WAVE = – – – – • RA: Register A RA contains the Register A value in real time. AT91M63200 128 – – – – – – ...
Page 129
... Read/Write 31 30 – – – – • RC: Register C RC contains the Register C value in real time – – – – – – – – – – – – AT91M63200 – – – – – – – – – – – – 129 ...
Page 130
... TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. AT91M63200 130 – ...
Page 131
... No effect Enables the RB Load Interrupt. • ETRGS: External Trigger effect Enables the External Trigger Interrupt – – – – – – – – – LDRAS CPCS CPBS AT91M63200 – – – – – – – – – CPAS LOVRS COVFS 131 ...
Page 132
... No effect Disables the RC Compare Interrupt. • LDRAS: RA Loading effect Disables the RA Load Interrupt (if WAVE = 0). • LDRBS: RB Loading effect Disables the RB Load Interrupt (if WAVE = 0). • ETRGS: External Trigger effect Disables the External Trigger Interrupt. AT91M63200 132 – – – – – – ...
Page 133
... The Load RB Interrupt is enabled. • ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled The External Trigger Interrupt is enabled – – – – – – – – – LDRAS CPCS CPBS AT91M63200 – – – – – – – – – CPAS LOVRS COVFS 133 ...
Page 134
... Clock Mode Register 0x08 Control Register 0x0C Status Register AT91M63200 134 The Watchdog timer has a 16-bit down counter. Bits 12-15 of the value loaded when the Watchdog is restarted are programmable using the HPVC parameter in WD_CMR (Clock Mode). Four clock sources are available to the Watchdog counter: MCKI/32, MCKI/128, MCKI/1024 or MCKI/4096 ...
Page 135
... OKEY: Overflow Access Key Used only when writing WD_OMR. OKEY is read as 0. 0x234 = Write access in WD_OMR is allowed. Other value = Write access in WD_OMR is prohibited – – – – – – OKEY EXTEN AT91M63200 – – – – – – IRQEN RSTEN WDEN 135 ...
Page 136
... Counter is preloaded when Watchdog counter is restarted with bits set (FFF) and bits equaling HPCV. • CKEY: Clock Access Key Used only when writing WD_CMR. CKEY is read as 0. 0x06E: Write access in WD_CMR is allowed. Other value: Write access in WD_CMR is prohibited. AT91M63200 136 – ...
Page 137
... RSTKEY RSTKEY – – – – – – – – – – – – AT91M63200 – – – – – – – – – – – – – – – – – WDOVF 137 ...
Page 138
... Disable the Watchdog by clearing the bit WDEN: Write 0x2340 to WD_OMR. This step is unnecessary if the WD is already disabled (reset state). 2. Initialize the WD Clock Mode Register: Write 0x373C to WD_CMR (HPCV = 15 and WDCLKS = MCK/8). AT91M63200 138 3. Restart the timer: Write 0xC071 to WD_CR. 4. Enable the Watchdog: Write 0x2345 to WD_OMR (interrupt enabled). ...
Page 139
... Peripheral Clock Status Register AT91M63200 Peripheral Clocks The clock of each peripheral integrated in the AT91M63200 can be individually enabled and disabled by writing in the Peripheral Clock Enable (PMC_PCER) and Peripheral Clock Disable Registers (PMC_PCDR). The status of the peripheral clocks can be read in the Peripheral Clock Sta- tus Register (PMC_PCSR) ...
Page 140
... Register Name: PMC_SCDR Access Type: Write only 31 30 – – – – – – – – • CPU: CPU Clock Disable effect Disables the CPU (ARM core) clock. AT91M63200 140 – – – – – – – – – – – ...
Page 141
... CPU: CPU Clock Status 0 = CPU clock is enabled CPU clock is disabled – – – – – – – – – – – – AT91M63200 – – – – – – – – – – – CPU 141 ...
Page 142
... Enables the TC4 clock. • TC5: TC5 Clock. Enable effect Enables the TC5 clock. • PIOA: PIOA Clock. Enable effect Enables the PIOA clock. • PIOB: PIOB Clock. Enable effect Enables the PIOB clock. AT91M63200 142 – – – – – ...
Page 143
... Disables the Parallel IO A clock. • PIOB: PIOB Clock. Disable effect Disables the Parallel IO B clock – – – – – – PIOA – TC5 SPI US2 US1 AT91M63200 – – – – – – TC4 TC3 TC2 US0 – – 143 ...
Page 144
... TC4 clock is enabled. • TC5: TC5 Clock Status 0 = TC5 clock is disabled TC5 clock is enabled. • PIOA: PIOA Clock Status 0 = PIOA clock is disabled PIOA clock is enabled. • PIOB: PIOB Clock Status 0 = PIOB clock is disabled PIOB clock is enabled. AT91M63200 144 – – – – – ...
Page 145
... VERSION: Version of the chip This value is incremented by one with each new version of the chip (from zero to a maximum value of 31 NVPTYP AT91M63200 Name Access SF_CIDR Read only SF_EXID Read only SF_RSR Read only – – – – – – SF_PMR Read/Write ...
Page 146
... Series (Mask ROM or ROM less “C” Series (Programmable Flash through Parallel Port “S” Series (Programmable Flash through Serial Port Reserved • EXT: Extension Flag 0 = Chip ID has a single register definition without extensions extended chip ID exists (to be defined in the future). AT91M63200 146 ...
Page 147
... The Advanced Interrupt Controller runs in protect mode. See “Protect Mode” on page 42 – – – – – – – – – RESET PMRKEY PMRKEY – – – AIC – – AT91M63200 – – – – – – – – – – – – – – – 147 ...
Page 148
... The Boundary Scan Register (BSR) contains 303 bits which correspond to active pins and associated control sig- nals. Each AT91M63200 input pin has a corresponding bit in the Boundary Scan Register for observability. Each AT91M63200 output pin has a corresponding 2-bit register in the BSR. The OUTPUT bit contains data which can be forced on the pad ...
Page 149
... OUTPUT 185 INOUT INPUT 184 OUTPUT 183 INOUT INPUT 182 OUTPUT 181 INOUT INPUT 180 OUTPUT 179 INOUT INPUT AT91M63200 Associated Pin Name Pin Type BSR Cells OUTPUT MPI_D1 INOUT OUTPUT MPI_D0 INOUT MPI_D[7:0] INOUT OUTPUT MPI_BG OUTPUT MPI_BR INPUT MPI_RNW ...
Page 150
... PA17/SCK1 155 154 153 PA16/RXD0 152 151 150 PA15/TXD0 149 148 147 PA14/SCK0 146 AT91M63200 150 Table 19. JTAG Boundary Scan Register (Continued) Associated Bit Pin Type BSR Cells Number OUTPUT 145 INOUT INPUT 144 CTRL 143 OUTPUT 142 ...
Page 151
... CTRL 56 OUTPUT 55 INOUT INPUT 54 CTRL 53 OUTPUT 52 INOUT INPUT 51 CTRL 50 OUTPUT 49 INOUT INPUT 48 CTRL 47 46 AT91M63200 Associated Pin Name Pin Type BSR Cells OUTPUT PB19/TCLK0 INOUT D15 INOUT OUTPUT D14 INOUT OUTPUT D13 INOUT OUTPUT D12 INOUT OUTPUT D11 INOUT OUTPUT D10 ...
Page 152
... A14 27 A13 26 A12 25 A11 24 A10 A[15: NLB/A0 12 A[7:0] 11 NCS3 AT91M63200 152 Table 19. JTAG Boundary Scan Register (Continued) Associated Bit Pin Type BSR Cells Number INPUT 10 INOUT OUTPUT 9 INOUT CTRL 8 OUTPUT 7 OUTPUT CTRL 6 OUTPUT 5 OUTPUT CTRL 4 OUTPUT 3 OUTPUT CTRL 2 OUTPUT OUTPUT 1 CTRL ...
Page 153
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