AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 74
AT91M63200-25AI
Manufacturer Part Number
AT91M63200-25AI
Description
IC ARM7 MCU 176 TQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91M43300-25CI.pdf
(21 pages)
2.AT91M43300-25CI.pdf
(5 pages)
3.AT91M63200-25AI.pdf
(12 pages)
4.AT91M63200-25AI.pdf
(153 pages)
Specifications of AT91M63200-25AI
Core Processor
ARM7
Core Size
16/32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, WDT
Number Of I /o
58
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
176-TQFP, 176-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
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- AT91M43300-25CI PDF datasheet
- AT91M43300-25CI PDF datasheet #2
- AT91M63200-25AI PDF datasheet #3
- AT91M63200-25AI PDF datasheet #4
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Receiver
Asynchronous Receiver
The USART is configured for asynchronous operation
when SYNC = 0 (bit 7 of US_MR). In asynchronous mode,
the USART detects the start of a received character by
sampling the RXD signal until it detects a valid start bit. A
low level (space) on RXD is interpreted as a valid start bit if
it is detected for more than 7 cycles of the sampling clock,
which is 16 times the baud rate. Hence, a space which is
longer than 7/16 of the bit period is detected as a valid start
bit. A space which is 7/16 of a bit period or shorter is
Figure 41. Asynchronous Mode: Start Bit Detection
Figure 42. Asynchronous Mode: Character Reception
74
Rate Clock
16 x Baud
Sampling
Example: 8-bit, parity enabled 1 stop
Sampling
RXD
AT91M63200
RXD
periods
0.5-bit
True Start Detection
period
1-bit
D0
D1
True Start
Detection
D2
D3
ignored and the receiver continues to wait for a valid start
bit.
When a valid start bit has been detected, the receiver sam-
ples the RXD at the theoretical mid-point of each bit. It is
assumed that each bit lasts 16 cycles of the sampling clock
(1-bit period) so the sampling point is 8 cycles (0.5-bit peri-
ods) after the start of the bit. The first sampling point is
therefore 24 cycles (1.5-bit periods) after the falling edge of
the start bit was detected. Each subsequent bit is sampled
16 cycles (1-bit period) after the previous one.
D4
D5
D6
D7
Parity Bit
Stop Bit
D0
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