AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 134

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

WD: Watchdog Timer
The AT91 series microcontrollers have an internal Watch-
dog timer which can be used to prevent system lock-up if
the software becomes trapped in a deadlock. In normal
operation the user reloads the Watchdog at regular inter-
vals before the timer overflow occurs. If an overflow does
occur, the Watchdog timer generates one or a combination
of the following signals, depending on the parameters in
WD_OMR (Overflow Mode Register):
•
•
•
Figure 58. Watchdog Timer Block Diagram
WD User Interface
WD Base Address: 0xFFFF8000
Table 16. WD Memory Map
134
If RSTEN is set, an internal reset is generated
(WD_RESET as shown in Figure 58). See also
“Watchdog Reset” on page 9.
If IRQEN is set, a pulse is generated on the signal
WDIRQ, which is connected to the Advanced Interrupt
Controller.
If EXTEN is set, a low level is driven on the NWDOVF
signal for a duration of 8 MCKI cycles.
Offset
0x0C
0x00
0x04
0x08
MCKI/1024
MCKI/4096
MCKI/128
MCKI/32
WD_RESET
Advanced
Bus (APB)
Peripheral
AT91M63200
Register
Overflow Mode Register
Clock Mode Register
Control Register
Status Register
WDIRQ
Clock Select
Control Logic
CLK_CNT
The Watchdog timer has a 16-bit down counter. Bits 12-15
of the value loaded when the Watchdog is restarted are
programmable using the HPVC parameter in WD_CMR
(Clock Mode). Four clock sources are available to the
Watchdog counter: MCKI/32, MCKI/128, MCKI/1024 or
MCKI/4096. The selection is made using the WDCLKS
parameter in WD_CMR. This provides a programmable
time-out period of 4ms to 8s with a 33 MHz system clock.
All write accesses are protected by control access keys to
help prevent corruption of the Watchdog should an error
condition occur. To update the contents of the mode and
control registers, it is necessary to write the correct bit pat-
tern to the control access key bits at the same time as the
control bits are written (the same write access).
Clear
WD_OMR
WD_CMR
WD_CR
WD_SR
Name
Programmable
Overflow
Down Counter
16-bit
Read/Write
Read/Write
Write only
Read only
Access
NWDOVF
Reset State
0
0
–
0