AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 41

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Hardware Interrupt Vectoring
The hardware interrupt vectoring reduces the number of
instructions to reach the interrupt handler to only one. By
storing the following instruction at address 0x00000018,
the processor loads the program counter with the interrupt
handler address stored in the AIC_IVR register. Execution
is then vectored to the interrupt handler corresponding to
the current interrupt.
The current interrupt is the interrupt with the highest priority
when the Interrupt Vector Register (AIC_IVR) is read. The
value read in the AIC_IVR corresponds to the address
stored in the Source Vector Register (AIC_SVR) of the cur-
rent interrupt. Each interrupt source has its corresponding
AIC_SVR. In order to take advantage of the hardware inter-
rupt vectoring, it is necessary to store the address of each
interrupt handler in the corresponding AIC_SVR at system
initialization.
Priority Controller
The NIRQ line is controlled by an 8-level priority encoder.
Each source has a programmable priority level of 7 to 0.
Level 7 is the highest priority and level 0 the lowest.
When the AIC receives more than one unmasked interrupt
at a time, the interrupt with the highest priority is serviced
first. If both interrupts have equal priority, the interrupt with
the lowest interrupt source number (see Table 7) is ser-
viced first.
The current priority level is defined as the priority level of
the current interrupt at the time the register AIC_IVR is
read (the interrupt which will be serviced).
In the case when a higher priority unmasked interrupt
occurs while an interrupt already exists, there are two pos-
sible outcomes depending on whether the AIC_IVR has
been read.
•
•
W h e n t h e E n d o f I n t e r r u p t C o m m a n d R e g i s t e r
(AIC_EOICR) is written, the current interrupt level is
updated with the last stored interrupt level from the stack (if
any). Hence, at the end of a higher priority interrupt, the
AIC returns to the previous state corresponding to the pre-
ceding lower priority interrupt which had been interrupted.
If the NIRQ line has been asserted but the AIC_IVR has
not been read, then the processor will read the new
higher priority interrupt handler address in the AIC_IVR
register and the current interrupt level is updated.
If the processor has already read the AIC_IVR, then the
NIRQ line is reasserted. When the processor has
authorized nested interrupts to occur and reads the
AIC_IVR again, it reads the new, higher priority interrupt
handler address. At the same time, the current priority
value is pushed onto a first-in last-out stack and the
current priority is updated to the higher priority.
ldrPC,[PC,# -&F20]
Interrupt Handling
The interrupt handler must read the AIC_IVR as soon as
possible. This de-asserts the NIRQ request to the proces-
sor and clears the interrupt in case it is programmed to be
edge triggered. This permits the AIC to assert the NIRQ
line again when a higher priority unmasked interrupt
occurs.
At the end of the interrupt service routine, the End of Inter-
rupt Command Register (AIC_EOICR) must be written.
This allows pending interrupts to be serviced.
Interrupt Masking
Each interrupt source, including FIQ, can be enabled or
disabled using the command registers AIC_IECR and
AIC_IDCR. The interrupt mask can be read in the read-only
register AIC_IMR. A disabled interrupt does not affect the
servicing of other interrupts.
Interrupt Clearing and Setting
All interrupt sources which are programmed to be edge trig-
gered (including FIQ) can be individually set or cleared by
respectively writing to the registers AIC_ISCR and
AIC_ICCR. This function of the interrupt controller is avail-
able for auto-test or software debug purposes.
Fast Interrupt Request
The external FIQ line is the only source which can raise a
fast interrupt request to the processor. Therefore, it has no
priority controller.
The external FIQ line can be programmed to be positive- or
negative-edge triggered or high- or low-level sensitive in
the AIC_SMR0 register.
The fast interrupt handler address can be stored in the
AIC_SVR0 register. The value written into this register is
available by reading the AIC_FVR register when an FIQ
interrupt is raised. By storing the following instruction at
address 0x0000001C, the processor will load the program
counter with the interrupt handler address stored in the
AIC_FVR register.
Alternatively, the interrupt handler can be stored starting
from address 0x0000001C as described in the ARM7TDMI
datasheet.
Software Interrupt
Interrupt source 1 of the advanced interrupt controller is a
software interrupt. It must be programmed to be edge trig-
gered in order to set or clear it by writing to the AIC_ISCR
and AIC_ICCR.
This is totally independent of the SWI instruction of the
ARM7TDMI processor.
ldrPC,[PC,# -&F20]
AT91M63200
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