AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 110

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

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110
SCBR: Serial Clock Baud Rate
In master mode, the SPI interface uses a modulus counter to derive the SPCK baud rate from the SPI master clock
(selected between MCKI and MCKI/32). The baud rate is selected by writing a value from 2 to 255 in the field SCBR.
The following equation determines the SPCK baud rate:
Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state
value. No serial transfers may occur. At reset, baud rate is disabled.
DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equation determines the delay:
DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip
select. The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, a delay of four SPI master clock periods are inserted.
Otherwise, the following equation determines the delay:
NPCS_to_SPCK_Delay = DLYBS * SPI_Master_Clock_period
Delay_After_Transfer = 32 * DLYBCT * SPI_Master_Clock_period
SPCK_Baud_Rate =
AT91M63200
SPI_Master_Clock_frequency
2 x SCBR