AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 55

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

PIO: Parallel I/O Controller
The AT91M63200 has 58 programmable I/O lines. 14 pins
on the AT91M63200 are dedicated as general-purpose I/O
pins. Other I/O lines are multiplexed with an external signal
of a peripheral to optimize the use of available package
pins (see Tables 9 and 10). These lines are controlled by
two separate and identical PIO Controllers called PIOA and
PIOB. Each PIO controller also provides an internal inter-
rupt signal to the Advanced Interrupt Controller.
Note: After a hardware reset, the PIO clock is disabled by
default (see “Power Management Controller” on page 139).
The user must configure the Power Management Controller
before any access to the user interface of the PIO.
Multiplexed I/O Lines
Some I/O lines are multiplexed with an I/O signal of a
peripheral. After reset, the pin is controlled by the PIO Con-
troller and is in input mode.
When a peripheral signal is not used in an application, the
corresponding pin can be used as a parallel I/O. Each par-
allel I/O line is bi-directional, whether the peripheral defines
the signal as input or output. Figure 38 shows the multi-
plexing of the peripheral signals with parallel I/O signals.
If a pin is multiplexed between the PIO Controller and a
peripheral, the pin is controlled by the registers PIO_PER
(PIO Enable) and PIO_PDR (PIO Disable). The register
PIO_PSR (PIO Status) indicates whether the pin is con-
trolled by the corresponding peripheral or by the PIO Con-
troller.
If a pin is a general-purpose parallel I/O pin (not multi-
plexed with a peripheral), PIO_PER and PIO_PDR have no
effect and PIO_PSR returns 1 for the bits corresponding to
these pins.
When the PIO is selected, the peripheral input line is con-
nected to zero.
Output Selection
The user can enable each individual I/O signal as an output
wi th th e re gi s ter s PIO _ O ER ( O ut pu t E na bl e) an d
PIO_ODR (Output Disable). The output status of the I/O
signals can be read in the register PIO_OSR (Output Sta-
tus). The direction defined has an effect only if the pin is
configured to be controlled by the PIO Controller.
I/O Levels
Each pin can be configured to be driven high or low. The
level is defined in four different ways, according to the fol-
lowing conditions.
If a pin is controlled by the PIO Controller and is defined as
an output (see “Output Selection” above), the level is pro-
grammed using the registers PIO_SODR (Set Output Data)
and PIO_CODR (Clear Output Data). In this case, the pro-
grammed value can be read in PIO_ODSR (Output Data
Status).
If a pin is controlled by the PIO Controller and is not defined
as an output, the level is determined by the external circuit.
If a pin is not controlled by the PIO Controller, the state of
the pin is defined by the peripheral (see peripheral
datasheets).
In all cases, the level on the pin can be read in the register
PIO_PDSR (Pin Data Status).
Filters
Optional input glitch filtering is available on each pin and is
controlled by the registers PIO_IFER (Input Filter Enable)
and PIO_IFDR (Input Filter Disable). The input glitch filter-
ing can be selected whether the pin is used for its periph-
eral function or as a parallel I/O line. The register
PIO_IFSR (Input Filter Status) indicates whether or not the
filter is activated for each pin.
Interrupts
Each parallel I/O can be programmed to generate an inter-
rupt when a level change occurs. This is controlled by the
PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Dis-
able) registers which enable/disable the I/O interrupt by
setting/clearing the corresponding bit in the PIO_IMR.
When a change in level occurs, the corresponding bit in the
PIO_ISR (Interrupt Status) is set whether the pin is used as
a PIO or a peripheral and whether it is defined as input or
output. If the corresponding interrupt in PIO_IMR (Interrupt
Mask) is enabled, the PIO interrupt is asserted.
When PIO_ISR is read, the register is automatically
cleared.
User Interface
Each individual I/O is associated with a bit position in the
Parallel I/O User Interface Registers. Each of these regis-
ters is 32 bits wide. If a parallel I/O line is not defined, writ-
ing to the corresponding bits has no effect. Undefined bits
read as zero.
Multi-driver (Open Drain)
Each I/O can be programmed for multi-driver option. This
means that the I/O is configured as open drain (can only
drive a low level) in order to support external drivers on the
same pin. An external pull-up is necessary to guarantee a
logic level of one when the pin is not being driven.
R e g i s t e r s P I O _ M D E R ( M u l t i - d r i v e r E n a b l e ) a n d
PIO_MDDR (Multi-driver Disable) control this option. Multi-
driver can be selected whether the I/O pin is controlled by
the PIO Controller or the peripheral. PIO_MDSR (Multi-
driver Status) indicates which pins are configured to sup-
port external drivers.
AT91M63200
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