AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet
AT91M63200-25AI
Specifications of AT91M63200-25AI
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AT91M63200-25AI Summary of contents
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... I/O Operating Voltage Range • -40°C to +85°C Operating Temperature Range • AT91M63200 in a 176-lead TQFP Package; AT91M43300 in a 144-ball BGA Package Description The AT91M63200 and AT91M43300 are members of the Atmel AT91 16/32-bit micro- controller family which is based on the ARM7TDMI processor core. ...
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... Static Current SC Notes: 1. See Table Output current. O AT91M63200/M43300 2 *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or other con- ditions beyond those indicated in the operational sections of this specification is not implied ...
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Power Consumption The values in the following tables are measured values in the operating conditions indicated (i.e. V 3.3V or 1.8V ° ). They represent the power consumption on the V Table 1. Core Power Consumption Mode ...
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... Although the core may be supplied between 1.8V and 3.6V, there are two voltage ranges that have been characterized for timing purposes. These are from 1.8V to 2.2V (core at 2V), and 2.7V to 3.6V (core at 3.3V). Timing values are given for both sets of condi- tions Table 4. Table 4. Voltage Ranges for Timing Characterization Condition Core at 2V Core at 3.3V AT91M63200/M43300 4 PAD ) 50pF – Industrial V ...
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Clock Waveforms Table 5. Clock Waveform Parameters Symbol Parameter 1/(t ) Oscillator Frequency CP t Main Clock Period CP t High Time CH t Low Time CL t Rising Edge r t Falling Edge f Table 6. Clock Propagation Times ...
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... NWR High to A23 - A1, NUB/NLB/A0, 19 NCS, CS Changes (No Wait States) EBI NWR High to A23 - A1, NCS Changes (Wait States) EBI Data Out Valid before NWR High 21 EBI Data Out Valid after NWR High 22 AT91M63200/M43300 6 Minimum Core at 2V Core at 3.3V Core at 2V TBD TBD TBD TBD TBD 5 TBD ...
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Table 9. EBI Read Signals Symbol Parameter EBI MCKI Falling to NRD Valid 13 EBI MCKI Rising to NRD Valid 14 EBI D0 - D15 in Setup before MCKI Falling 15 EBI D0 - D15 in Hold after MCKI Falling ...
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... Figure 3. EBI Signals Relative to MCKI MCKI NCS A23 NWAIT NUB/NLB/A0 (1) NRD (2) NRD D0 - D15 read NWR (No Wait States) NWR (Wait States D15 to Write Notes: 1. Early Read Protocol 2. Standard Read Protocol AT91M63200/M43300 8 EBI 5 EBI /EBI Wait EBI EBI 6 7 EBI /EBI 1 2 EBI ...
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Peripheral Signals Relative to MCKI USART Signals Table 10. USART Outputs Symbol Parameter US MCKI Rising to SCK Output 1 Rising/Falling US MCKI Rising to TXD Toggling 2 US SCK Output Falling to TXD Toggling 3 US SCK Input Falling ...
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... Figure 4. USART Signals Relative to MCKI MCKI SCK Output SCK Input TXD RXD RXD/SCK (Asynchronous) AT91M63200/M43300 ...
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SPI Signals Table 14. SPI Signals in Master Mode Symbol Parameter t SPI Operating Period SPCK f SPI Operating Frequency SPCK SP Delay before NPCS[3: Delay between Chip Selects 2 SP Delay before SPCK 3 SP MISO/SPCK Setup ...
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... Table 17. Asynchronous Timer Input Minimum Pulse-width Symbol Type of Inputs TC Asynchronous 9 Table 18. Asynchronous Timer Input Minimum Input Period Symbol Type of Inputs TC Asynchronous 10 AT91M63200/M43300 Waveform Total-count Detection mode. In addition CP Core at Parameter TCLK/TIOA/TIOB Minimum Pulse-width Parameter TCLK/TIOA/TIOB Minimum Input Period Maximum Core at 2V Core at 3.3V ...
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Figure 6. Timer Relative to MCKI MCKI TIOA/TIOB/TCLK Asynchronous In TC TCLK Synchronous Input TC 5H TIOA/TIOB Synchronous Inputs TC 1 TIOA Output TC TIOB Output 3(t /2) CP Detect ...
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... A minimum pulse width is necessary as shown in Table 21 and as represented in Figure 8. Table 21. Reset Minimum Pulse-width Symbol Parameter RST NRST Minimum Pulse-width 3 Figure 8. Reset Signals Relative to MCKI MCKI NRST Only the NRST rising edge is synchronized. The falling edge is asynchronous. AT91M63200/M43300 14 Core at 2V TBD TBD RST 1H RST ...
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Advanced Interrupt Controller Signals The inputs can be used synchronously or asynchronously (in relation to MCKI). For synchronous AIC inputs, certain setup/hold constraints must be met. These constraints are shown in Table 22 and are represented in Figure 9. For ...
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... Table 27. PIO Asynchronous Input Minimum Pulse-width Symbol Type Parameter PIO Asynchronous PIO Input Minimum Pulse-width 5 Figure 10. PIO Signals Relative to MCKI MCKI PIO 3H PIO Synchronous Inputs PIO Asynchronous Inputs PIO Outputs AT91M63200/M43300 16 Maximum Core at 2V TBD TBD Setup Core Core 3.3V TBD 2 TBD 2 PIO PIO 3S ...
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... Multi-processor Interface Signals (AT91M63200 Only) Figure 11. External Arbitration MPI_BR MPI_BG MPI_D[15:0] Table 28. External Arbitration Symbol Parameter MPI_BR High to MPI_BG High Delay t 1 (30 pf) t MPI_BR Low to MPI_BG Low Data Transfer Minimum Core at 2V Core at 3. Maximum Core at 2V Core at 3.3V Units TBD ...
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... UBLZ t Chip Deselect to Output in High-Z CHZ t Output Disable to Output in High-Z OHZ t LBHZ, Byte Deselect to Output in High-Z t UBHZ Figure 12. MPI Read Access MPI_A[9:1] MPI_NCS MPI_NOE MPI_NLB, MPI_NUB MPI_D[15:0] AT91M63200/M43300 18 Minimum Core at 2V Core at 3.3V TBD 22 TBD 0 TBD 0 TBD 0 TBD Valid Address t AA ...
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Table 30. MPI Write Access Symbol Parameter t Write Cycle Time WC t Address Valid to End of Write AW t Chip Select to End of Write CW t Write pulse-width Byte Select to End of Write ...
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... Figure 14. MPI Write Access (MPI_NCS Controlled) MPI_A[9:1] MPI_RNW MPI_NCS MPI_NLB, MPI_NUB MPI_Din[15:0] Figure 15. MPI Write Access (MPI_NLB, MPI_NUB Controlled) MPI_A[9:1] MPI_RNW MPI_NCS MPI_NLB, MPI_NUB MPI_Din[15:0] AT91M63200/M43300 Valid Address LBW UBW t DW High-Z Valid Data t WC Valid Address LBW UBW t DW High-Z ...
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... No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. ...