HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 685

MCU 3/5V 60K PB-FREE 84-PLCC

HD64F3337YCP16V

Manufacturer Part Number
HD64F3337YCP16V
Description
MCU 3/5V 60K PB-FREE 84-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheets

Specifications of HD64F3337YCP16V

Core Size
8-Bit
Program Memory Size
60KB (60K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
No. Of I/o's
74
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
6
No. Of Pwm Channels
2
Digital Ic Case Style
PLCC
Controller Family/series
H8/300
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3337YCP16V
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COILMASTER
Quantity:
30 000
Part Number:
HD64F3337YCP16V
Manufacturer:
RENESAS
Quantity:
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Part Number:
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SYSCR—System Control Register
Bit
Initial value
Read/Write
Software Standby
0
1
SSBY
R/W
SLEEP instruction causes transition to sleep mode. (initial value)
SLEEP instruction causes transition to software standby mode.
7
0
Standby Timer Select 2 to 0 (ZTAT and Mask ROM Versions)
Standby Timer Select 2 to 0 (F-ZTAT Version)
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
STS2
R/W
0
1
0
1
0
1
0
1
0
1
External Reset
6
0
0
1
Clock settling time = 8,192 states (initial value)
Clock settling time = 16,384 states
Clock settling time = 32,768 states
Clock settling time = 65,536 states
Clock settling time = 131,072 states
Unused
Settling time = 8,192 states (initial value)
Settling time = 16,384 states
Settling time = 32,768 states
Settling time = 65,536 states
Settling time = 131,072 states
Settling time = 1,024 states
Unused
Reset was caused by watchdog timer overflow
Reset was caused by external reset signal (initial value)
NMI Edge
0
1
STS1
R/W
Falling edge of NMI is detected.
Rising edge of NMI is detected.
5
0
Host Interface Enable
0
1
Host interface is prohibited (initial value)
Host interface is allowed (slave mode)
STS0
R/W
4
0
RAM Enable
0
1
On-chip RAM is disabled.
On-chip RAM is enabled. (initial value)
XRST
R
3
1
H'C4
NMIEG
R/W
2
0
R/W
HIE
1
0
System Control
RAME
R/W
0
1
653

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