HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 390

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16.3
The D/A converter module has two built-in D/A converter circuits that can operate independently.
D/A conversion is performed continuously whenever enabled by the D/A control register. When a
new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The
converted result is output by setting the DAOE0 or DAOE1 bit to 1.
An example of conversion on channel 0 is given next. Figure 16.2 shows the timing.
1. Software writes the data to be converted in DADR0.
2. D/A conversion begins when the DAOE0 bit in DACR is set to 1. After a conversion delay,
3. If a new value is written in DADR0, conversion begins immediately. Output of the converted
4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
358
ø
Address
DADR0
DAOE0
DA0
t
DCONV
analog output appears at the DA0 pin. The output value is AV
This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0.
result begins after the conversion delay time.
: D/A conversion time
Operation
DADR0
write cycle
High-impedance state
DACR
write cycle
Figure 16.2 D/A Conversion (Example)
Conversion data (1)
t
DCONV
Conversion result (1)
DADR0
write cycle
CC
(DADR0 value)/256.
t
DCONV
Conversion data (2)
Conversion result (2)
DACR
write cycle