HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 201

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit 7—Input Edge Select A (IEDGA): This bit selects the rising or falling edge of the input
capture A signal (FTIA).
Bit 7: IEDGA
0
1
Bit 6—Input Edge Select B (IEDGB): This bit selects the rising or falling edge of the input
capture B signal (FTIB).
Bit 6: IEDGB
0
1
Bit 5—Input Edge Select C (IEDGC): This bit selects the rising or falling edge of the input
capture C signal (FTIC).
Bit 5: IEDGC
0
1
Bit 4—Input Edge Select D (IEDGD): This bit selects the rising or falling edge of the input
capture D signal (FTID).
Bit 4: IEDGD
0
1
Bit 3—Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for
ICRA.
Bit 3: BUFEA
0
1
Description
Input capture A events are recognized on the falling edge of FTIA. (Initial value)
Input capture A events are recognized on the rising edge of FTIA.
Description
Input capture B events are recognized on the falling edge of FTIB. (Initial value)
Input capture B events are recognized on the rising edge of FTIB.
Description
Input capture C events are recognized on the falling edge of FTIC. (Initial value)
Input capture C events are recognized on the rising edge of FTIC.
Description
Input capture D events are recognized on the falling edge of FTID. (Initial value)
Input capture D events are recognized on the rising edge of FTID.
Description
ICRC is used for input capture C.
ICRC is used as a buffer register for input capture A.
(Initial value)
169