HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 330

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

13.3.3
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits the data. The receive procedure and operations in
master receive mode are described below. See also figure 13.7.
1. Clear TRS to 0 in ICCR to switch from transmit mode to receive mode.
2. Read ICDR to start receiving. When ICDR is read, a receive clock is output in synchronization
3. When 1 byte of data has been received, IRIC is set to 1 in ICSR at the rise of the ninth receive
4. Software clears IRIC to 0 in ICSR.
5. When ICDR is read, receiving of the next data starts in synchronization with the internal clock.
Steps 3 to 5 can be repeated to receive data continuously. To stop receiving, set TRS to 1, read
ICDR, then write write 0 in BBSY and 0 in SCP in ICSR. This generates a stop condition by
causing a low-to-high transition of SDA while SCL is high. If it is not necessary to acknowledge
each bye of data, set ACKB to 1 in ICSR before receiving starts.
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with the internal clock, and data is received. At the ninth clock pulse the master device drives
SDA low to acknowledge the data.
clock pulse. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. After one frame has been
transferred, SCL is automatically brought to the low level in synchronization with the internal
clock and held low.
Master Receive Operation