HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 544

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Automatic Alignment of SCI Bit Rate
When started in boot mode, the H8/3337SF measures the low period in asynchronous SCI data
(H'00) transmitted from the host. The data format is eight data bits, one stop bit, and no parity bit.
From the measured low period (9 bits), the H8/3337SF computes the host’s bit rate. After aligning
its own bit rate, the H8/3337SF sends the host one byte of H'00 data to indicate that bit-rate
alignment is completed. The host should check that this alignment-completed indication is
received normally and send one H'55 byte back to the H8/3337SF. If the alignment-completed
indication is not received normally, the H8/3337F should be reset, then restarted in boot mode to
measure the low period again. There may be some alignment error between the host’s and
H8/3337SF’s bit rates, depending on the host’s transmission bit rate and the H8/3337SF’s system
clock frequency (f
4800, or 9600 bps.
Table 21.7 lists typical host transfer bit rates and indicates the system clock frequency ranges over
which the H8/3337SF can align its bit rate automatically. Boot mode should be used within these
frequency ranges.
Table 21.7 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by
Host Bit Rate
9600 bps
4800 bps
2400 bps
RAM Area Allocation in Boot Mode: In boot mode, the 128 bytes from H'FF00 to H'FF7F are
reserved for use by the boot program, as shown in figure 21.9. The user program is transferred into
the area from H'F780 to H'FDFF (1664 bytes). The boot program area can be used after the
transition to execution of the user program transferred into RAM. If a stack area is needed, set it
within the user program.
512
Figure 21.8 Measurement of Low Period in Data Transmitted from Host
Start
bit
H8/3337SF
OSC
). To have the SCI operate normally, set the host’s transfer bit rate to 2400,
D0
This low period (9 bits) is measured (H'00 data)
System Clock Frequencies (f
Alignment by H8/3337SF
8 MHz to 16 MHz
4 MHz to 16 MHz
2 MHz to 16 MHz
D1
D2
D3
D4
OSC
) Permitting Automatic Bit-Rate
D5
D6
D7
High for at
least 1 bit
Stop
bit