HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 154

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper
address output pins and general input pins. Each pin becomes an upper address output pin if its
P2DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins
are input pins. To be used for address output, their P2DDR bits must be set to 1. Figure 7.7 shows
the pin functions in mode 2.
Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected
individually. A pin becomes a general input pin when its P2DDR bit is cleared to 0, and a general
output pin when this bit is set to 1. Figure 7.8 shows the pin functions in mode 3.
122
Port 2
Figure 7.7 Pin Functions in Mode 2 (Port 2)
Figure 7.8 Pin Functions in Mode 3 (Port 2)
Port 2
When P2DDR = 1
A
A
A
A
A
A
A
A
15
14
13
12
11
10
9
8
(output)
(output)
(output)
(output)
(output)
(output)
(output)
(output)
P2
P2
P2
P2
P2
P2
P2
P2
7
6
5
4
3
2
1
0
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
(input/output)
When P2DDR = 0
P2
P2
P2
P2
P2
P2
P2
P2
7
6
5
4
3
2
1
0
(input)
(input)
(input)
(input)
(input)
(input)
(input)
(input)