HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 27

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

13.4 Application Notes.............................................................................................................. 309
Section 14 Host Interface (H8/3337 Series Only)
14.1 Overview............................................................................................................................ 315
14.2 Register Descriptions......................................................................................................... 319
14.3 Operation ........................................................................................................................... 326
14.4 Interrupts............................................................................................................................ 330
14.5 Application Note................................................................................................................ 331
Section 15 A/D Converter
15.1 Overview............................................................................................................................ 333
15.2 Register Descriptions......................................................................................................... 337
15.3 CPU Interface .................................................................................................................... 340
15.4 Operation ........................................................................................................................... 342
13.3.4 Slave Transmit Operation..................................................................................... 300
13.3.5 Slave Receive Operation ...................................................................................... 302
13.3.6 IRIC Set Timing and SCL Control....................................................................... 303
13.3.7 Noise Canceler...................................................................................................... 304
13.3.8 Sample Flowcharts ............................................................................................... 305
14.1.1 Block Diagram...................................................................................................... 316
14.1.2 Input and Output Pins........................................................................................... 317
14.1.3 Register Configuration ......................................................................................... 318
14.2.1 System Control Register (SYSCR) ...................................................................... 319
14.2.2 Host Interface Control Register (HICR) .............................................................. 319
14.2.3 Input Data Register 1 (IDR1) ............................................................................... 320
14.2.4 Output Data Register 1 (ODR1) ........................................................................... 321
14.2.5 Status Register 1 (STR1)...................................................................................... 321
14.2.6 Input Data Register 2 (IDR2) ............................................................................... 322
14.2.7 Output Data Register 2 (ODR2) ........................................................................... 323
14.2.8 Status Register 2 (STR2)...................................................................................... 323
14.2.9 Serial/Timer Control Register (STCR) ................................................................ 325
14.3.1 Host Interface Operation ...................................................................................... 326
14.3.2 Control States ....................................................................................................... 326
14.3.3 A
14.4.1 IBF1, IBF2............................................................................................................ 330
14.4.2 HIRQ
15.1.1 Features ................................................................................................................ 333
15.1.2 Block Diagram...................................................................................................... 334
15.1.3 Input Pins.............................................................................................................. 335
15.1.4 Register Configuration ......................................................................................... 336
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 337
15.2.2 A/D Control/Status Register (ADCSR)................................................................ 338
15.2.3 A/D Control Register (ADCR)............................................................................. 340
20
Gate ................................................................................................................ 327
11
, HIRQ
1
, and HIRQ
................................................................................................. 333
12
................................................................................ 330
...................................................... 315
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