HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 694

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

ICSR—I
662
Note: * Only 0 can be written, to clear the flag.
Bus Busy
Bit
Initial value
Read/Write
0
1
Bus is free
Cleared by detection
of a stop condition
Bus is busy
Set by detection
of a start condition
Start Condition/Stop Condition Prohibit
0
1
2
C Bus Status Register
Arbitration Lost Flag
0
1
Writing 0 issues a start or stop condition, in combination with BBSY
Reading always results in 1
Writing is ignored
Slave Address Recognition Flag
Bus arbitration won
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading AL = 1, then writing 0
Arbitration lost
Set if the internal SDA and bus line disagree at the rise of SCL in master transmit mode
Set if the internal SCL is high at the fall of SCL in master transmit mode
0
1
General Call Address Recognition Flag
0
1
Slave address or general call address not recognized (Initial value)
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading AAS = 1, then writing 0
Slave address or general call address recognized
Set when the slave address or general call address is detected in slave receive mode
General call address not recognized
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading ADZ = 1, then writing 0
General call address recognized
Set when the general call address is detected in slave receive mode
BBSY
Acknowledge Bit
R/W
0
1
7
0
Receive mode: 0 is output at acknowledge output timing
Transmit mode: indicates that the receiving device has acknowledged the data
Receive mode: 1 is output at acknowledge output timing
Transmit mode: indicates that the receiving device has not acknowledged the data
I
2
0
1
C Bus Interface Interrupt Request Flag
Waiting for transfer, or transfer in progress
Cleared by reading IRIC = 1, then writing 0
Interrupt requested
Set to 1 at the following times:
Master mode
• End of data transfer
• Bus arbitration lost
Slave mode (when FS = 0)
• When the slave address is matched, and whenever a data transfer ends after that,
• When a general call address is detected, and whenever a data transfer ends after
Slave mode (when FS = 1)
• End of data transfer
until a retransmit start condition or a stop condition is detected
that, until a retransmit start condition or a stop condition is detected
R/(W)*
IRIC
6
0
SCP
W
5
1
—
—
4
1
R/(W)*
AL
3
0
H'D9
R/(W)*
AAS
2
0
R/(W)*
ADZ
1
0
ACKB
R/W
0
0
I
2
C