HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 18

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section
Only) [Option]
13.4 Application Notes
15.6.6 Effect on Absolute
Accuracy
18.3.2 Notes on
Programming
21.1.7 Flash Memory
Operating Modes
21.2.3 Erase Block
Register 2 (EBR2)
21.3.1 Boot Mode
21.4 to 21.4.4
21.5.1 Writer Mode
Setting
21.5.3 Operation in
Writer Mode
21.6 Flash Memory
Programming and Erasing
Precautions
Page
309
352
371
500
501
502
507
512
513
516 to 520
524
534
536
537
Item
4. Note on Issuance of
5. Note on Issuance of Stop
6. Countermeasure
7. Additional Note
8. Precautions when Clearing
Figure 15.10 Example of
Analog Input Circuit
Figure 21.2 Flash Memory
Related State Transitions
Figure 21.3 Boot Mode
Figure 21.4 User
Programming Mode (Example)
RAM Area Allocation in Boot
Mode
Figure 21.9 RAM Areas in
Boot Mode
Notes on Use of Boot Mode
Figure 21.22 Status Read
Mode Timing Waveforms
Table 21.19 Status Read
Mode Return Codes
(1) Program with the specified
voltage and timing
Table 21.22 Area Accessed in
Each Mode with FLSHE = 0
Retransmission Start
Condition
Condition
the IRIC Flag when Using
the Wait Function
Description
(see Manual for details)
Added
Figure amended
(1) description added.
“SWE” amended to
“FLSHE”.
Procedure 2 amended.
Procedure 2 amended.
Bit 7 * and Note
description added.
Description amended.
Amended
5 description amended.
Entire description
amended.
* and Note description
added.
Note amended
Description amended.
FLSHE = 1 mode 2
amended