HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 489
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HD64F3337YCP16
Manufacturer Part Number
HD64F3337YCP16
Description
IC H8 MCU FLASH 60K 84PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
Package
84PLCC
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
74
Interface Type
HIF/I2C/SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3337YCP16
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
COILMASTER
Quantity:
30 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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20.4.6
Flowchart for Erasing One Block
Address + 1
Erasing Flowchart and Sample Program
address
No
(set bit of block to be erased to 1)
Dummy write to verify address
(flash memory latches address)
(clear bit of erased block to 0)
Write 0 data in all addresses
Verify
Clear erase block register
Enable watchdog timer
Select erase-verify mode
to be erased (prewrite)
Set top address in block
Set erase block register
Disable watchdog timer
(EV bit = 1 in FLMCR)
(E bit = 1 in FLMCR)
End of block erase
Select erase mode
as verify address
OK
Wait (t
*4
Wait (t
Last address?
Wait (x) ms
Clear EV bit
Clear E bit
(read data=H'FF?)
n = 1
Start
VS
VS
Figure 20.9 Erasing Flowchart
2) s
1) s
Yes
*5
*6
*6
*1
*2
*3
No go
Erasing ends
Clear EV bit
Erase error
Notes: *1 Program all addresses to be erased
n
N?
Yes
*6
*2 Set the watchdog timer overflow
*3 For the erase-verify dummy write,
*4 Read the data to be verified with a
*5 The erase time x is successively
*6 t
by following the prewrite flowchart.
interval to the value indicated in
table 20.8.
write H'FF with a byte transfer
instruction.
byte transfer instruction. When
erasing two or more blocks, clear
the bits of erased blocks in the
erase block registers, so that only
unerased blocks will be erased
again.
incremented by the initial set value
value of 6.25 ms or less should be
set, and the time for one erasure
should be 50 ms or less.
t
N:
VS
VS
2
1: 4 s or more
2: 2 s or more
n–1
602
(n = 1, 2, 3, 4). An initial
No
Erase-verify ends
Double erase time
n + 1
(x
n
2 x)
4?
n
No
Yes
457
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