HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 493
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
HD64F3337YCP16
Manufacturer Part Number
HD64F3337YCP16
Description
IC H8 MCU FLASH 60K 84PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
Package
84PLCC
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
74
Interface Type
HIF/I2C/SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3337YCP16
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
COILMASTER
Quantity:
30 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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ERASE:
LOOPE:
; Execute erase-verify
LOOPEV:
EVR2:
LOOPDW:
RERASE:
BRER:
OKEND:
ABEND2:
ADDS
MOV.W
MOV.W
MOV.W
BSET
NOP
NOP
NOP
NOP
SUBS
MOV.W
BNE
BCLR
MOV.W
MOV.W
MOV.W
MOV.B
BSET
DEC
BNE
MOV.B
MOV.B
MOV.B
DEC
BNE
MOV.B
CMP.B
BNE
CMP.W
BNE
BRA
BCLR
SUBS
MOV.W
CMP.W
BPL
ADD.W
MOV.W
CMP.W
BNE
BRA
BCLR
MOV.B
MOV.B
One block erased
Erase error
R4H
#1,
#H'e,
R4,
R5,
#1,
#1,
R4,
LOOPE
#1,
#H'A500,
R4,
R0,
#H'b,
#3,
LOOPEV
#H'FF,
R1H,
#H'c,
R4H
LOOPDW
@R3+,
#H'FF,
RERASE
R2,
EVR2
OKEND
#3,
#1,
#H'0004,
R4,
BRER
R5,
#H'025A,
R4,
ERASE
ABEND2
#3,
#H'00,
R6L,
R6
R4
@TCSR
R4
@FLMCR:8
R4
R4
@FLMCR:8
R4
@TCSR
R3
R4H
@FLMCR:8
R1H
@R3
R4H
R1H
R1H
R3
@FLMCR:8
R3
R4
R6
R5
R4
R6
@FLMCR:8
R6L
@EBR*:8
; Erase-verify fail counter + 1
;
; Start watchdog timer
; Set erase loop counter
;
;
; Wait loop
;
; Stop watchdog timer
; Top address of block to be erased
; Set erase-verify loop counter
;
; Wait loop
;
; Dummy write
; Set erase-verify loop counter
;
; Wait loop
; Read
; Read data = H'FF?
; If read data
; Last address of block?
; Erase-verify address – 1
;
; Erase-verify fail count executed 4 times?
; If R6
; If R6 < 4, Erase time
;
; Erase-verify executed 602 times?
; If erase-verify not executed 602 times, erase again
; If erase-verify executed 602 times, branch to ABEND2
;
;
;
;
;
;
;
Clear EBR*
4, branch to BRER (branch until R6 is 4 to 602)
H'FF, branch to RERASE
Set E bit
Clear E bit
Set EV bit
Clear EV bit
Clear EV bit
2 (execute when R6 is 1, 2, or 3)
R3
R6
461
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