HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 200
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HD64F3337YCP16
Manufacturer Part Number
HD64F3337YCP16
Description
IC H8 MCU FLASH 60K 84PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
Package
84PLCC
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
74
Interface Type
HIF/I2C/SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Bit 2—Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value
matches the OCRB value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 2: OCFB
0
1
Bit 1—Timer Overflow Flag (OVF): This status flag is set to 1 when FRC overflows (changes
from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 1: OVF
0
1
Bit 0—Counter Clear A (CCLRA): This bit selects whether to clear FRC at compare-match A
(when the FRC and OCRA values match).
Bit 0: CCLRA
0
1
8.2.6
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in the standby modes.
168
Bit
Initial value
Read/Write
Timer Control Register (TCR)
IEDGA
R/W
Description
To clear OCFB, the CPU must read OCFB after it has been set to 1, then write
a 0 in this bit.
This bit is set to 1 when FRC = OCRB.
Description
To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0
in this bit.
This bit is set to 1 when FRC changes from H'FFFF to H'0000.
Description
The FRC is not cleared.
The FRC is cleared at compare-match A.
7
0
IEDGB
R/W
6
0
IEDGC
R/W
5
0
IEDGD
R/W
4
0
BUFEA
R/W
3
0
BUFEB
R/W
2
0
CKS1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
CKS0
R/W
0
0
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