HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 498

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

; Execute erase-verify
EVR:
LOOPEV:
EBRTST:
EBR2EV:
ADD01:
ERASE1:
ERSEVF:
EVR2:
LOOPEP:
SBCLR:
BLKAD:
466
MOV.W
MOV.W
ADD.W
MOV.W
SUB.W
MOV.B
MOV.B
BSET
DEC
BNE
CMP.B
BEQ
CMP.B
BMI
MOV.B
SUBX
BTST
BNE
BRA
BTST
BNE
INC
MOV.W
BRA
BRA
MOV.W
MOV.B
MOV.B
MOV.B
DEC
BNE
MOV.B
CMP.B
BNE
MOV.W
CMP.W
BNE
CMP.B
BMI
MOV.B
SUBX
BCLR
BRA
BCLR
INC
BRA
#RAMSTR,
#ERVADR,
R3,
#START,
R3,
#H'00,
#H'b,
#3,
R4H
LOOPEV
#H'10,
HANTEI
#H'08,
EBR2EV
R1L,
#H'08,
R1H,
ERSEVF
ADD01
R1L,
ERSEVF
R1L
@R2+,
EBRTST
ERASE
@R2+,
#H'FF,
R1H,
#H'c,
R4H
LOOPEP
@R3+,
#H'FF,
BLKAD
@R2,
R4,
EVR2
#H'08,
SBCLR
R1L,
#H'08,
R1H,
BLKAD
R1L,
R1L
EBRTST
R2
R3
R2
R3
R2
R1L
R4H
@FLMCR:8
R1L
R1L
R1H
R1H
R0H
R0L
R3
R3
R1H
@R3
R4H
R1H
R1H
R4
R3
R1L
R1H
R1H
R0H
R0L
; Starting transfer destination address (RAM)
;
; #RAMSTR + #ERVADR
;
; Address of data area used in RAM
; Used to test R1L bit in R0
; Set erase-verify loop counter
;
; Wait loop
; R1L = H'10?
; If finished checking all R0 bits, branch to HANTEI
;
; Test EBR1 if R1L
;
; R1L – 8
; Test R1H bit in EBR1 (R0H)
; If R1H bit in EBR1 (R0H) is 1, branch to ERSEVF
; If R1H bit in EBR1 (R0H) is 0, branch to ADD01
; Test R1L bit in EBR2 (R0L)
; If R1L bit in EBR2 (R0H) is 1, branch to ERSEVF
; R1L + 1
; Dummy-increment R2
;
; Branch to ERASE via Erase 1
; Top address of block to be erase-verified
;
; Dummy write
; Set erase-verify loop counter
;
; Wait loop
; Read
; Read data = H'FF?
; If read data
; Top address of next block
; Last address of block?
; Test EBR1 if R1L
;
; R1L – 8
; Clear R1H bit in EBR1 (R0H)
; Clear R1L bit in EBR2 (R0L)
; R1L + 1
;
;
R1L
R1H
R1L
R1H
H'FF branch to BLKAD
Set EV bit
8, or EBR2 if R1L < 8
8, or EBR2 if R1L < 8
R2