HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 294

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

262
1
2
3
4
Start transmitting or receiving
Set CKE1 and CKE0 bits in
and set RIE, TIE, TEIE, and
Set TE or RE to 1 in SCR,
SCR (leaving TE and RE
Clear TE and RE bits to
Select communication
MPIE as necessary
Set value in BRR
format in SMR
cleared to 0)
1 bit interval
Initialization
0 in SCR
elapsed?
Figure 12.4 Sample Flowchart for SCI Initialization
Yes
No
1.
2.
3.
4.
Select interrupts and the clock source in the
serial control register (SCR). Leave TE and RE
cleared to 0. If clock output is selected, in
asynchronous mode, clock output starts
immediately after the setting is made in SCR.
Select the communication format in the serial
mode register (SMR).
Write the value corresponding to the bit rate in
the bit rate register (BRR). This step is not
necessary when an external clock is used.
Wait for at least the interval required to transmit
or receive one bit, then set TE or RE in the serial
control register (SCR). Setting TE or RE enables
the SCI to use the TxD or RxD pin.
Also set the RIE, TIE, TEIE, and MPIE bits as
necessary to enable interrupts. The initial states
are the mark transmit state, and the idle receive
state (waiting for a start bit).