HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 494

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Flowchart for Erasing Multiple Blocks
462
Erase-verify
next block
Address + 1
Address
No
Select erase mode (E bit = 1 in FLMCR)
No
Figure 20.11 Multiple-Block Erase Flowchart
(set bits of block to be erased to 1)
Write 0 data to all addresses to be
Dummy write to verify address
(flash memory latches address)
Clear EBR bit of erased block
Set top address of block as
Set erase block registers
Select erase-verify mode
Enable watchdog timer
Disable watchdog timer
(EV bit = 1 in FLMCR)
(EBR1 = EBR2 = 0?)
(read data = H'FF?)
erased (prewrite)
Yes
All blocks erased?
Yes
All erased blocks
Wait (t
Wait (t
verify address
OK
Wait (x)ms
End of erase
Yes
Clear EV bit
Last address
Clear E bit
verified?
in block?
Verify
Start
n = 1
VS
VS
2) s
1) s
*4
*5
*6
*6
*1
*2
*3
No go
No
Erasing ends
Double Erase time
All erased blocks
No
Yes
Erase error
(x
n
verified?
n
Notes: *1 Program all addresses to be
2 x)
N?
4?
Yes
*6
*2 Set the watchdog timer overflow
*3 For the erase-verify dummy
*4 Read the data to be verified with
*5 The erase time x is successively
*6 t
erased by following the prewrite
flowchart.
interval to the value indicated in
table 20.8.
write, write H'FF with a byte
transfer instruction.
a byte transfer instruction. When
erasing two or more blocks,
clear the bits of erased blocks in
the erase block register, so that
only unerased blocks will be
erased again.
incremented by the initial set
value
initial value of 6.25 ms or less
should be set, and the time for
one erasure should be 50 ms or
less.
t
N:
VS
VS
1: 4 s or more
2: 2 s or more
Erase-verify next block
Yes
602
No
2
n–1
No
(n = 1, 2, 3, 4). An
n + 1
n