HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 613
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HD64F3337YCP16
Manufacturer Part Number
HD64F3337YCP16
Description
IC H8 MCU FLASH 60K 84PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
Package
84PLCC
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
74
Interface Type
HIF/I2C/SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3337YCP16
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
COILMASTER
Quantity:
30 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 613 of 749
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Table 23.22 Timing Conditions of On-Chip Supporting Modules
Conditions: V
Item
FRT
TMR
PWM
SCI
Ports
HIF read
cycle
HIF write
cycle
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock pulse width
Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock pulse width (single
edge)
Timer clock pulse width (both
edges)
Timer output delay time
Input clock cycle
Transmit data delay time (Sync)
Receive data setup time (Sync)
Receive data hold time (Sync)
Input clock pulse width
Output data delay time
Input data setup time
Input data hold time
CS/HA
CS/HA
IOR pulse width
HDB delay time
HDB hold time
HIRQ delay time
CS/HA
CS/HA
IOW pulse width
High-speed GATE A
High-speed GATE A
HDB hold time
GA
Ta = –20˚C to +75˚C (regular specifications), Ta = –40 C to +85 C (wide-range
specifications)
CC
20
delay time
= 3.0 V to 5.5 V, V
0
0
0
0
setup time
setup time
hold time
hold time
(Async)
(Sync)
20
20
not uesd
uesd
SS
= 0 V, ø = 2.0 MHz to maximum operating frequency,
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
FTOD
FTIS
FTCS
FTCWH
FTCWL
TMOD
TMRS
TMCS
TMCWH
TMCWL
PWOD
Scyc
TXD
RXS
RXH
SCKW
PWD
PRS
PRH
HAR
HRA
HRPW
HRD
HRF
HIRQ
HAW
HWA
HWPW
HDW
HWD
HGA
Min
—
80
80
1.5
—
80
80
1.5
2.5
—
4
6
—
150
150
0.4
—
80
80
10
10
220
—
0
—
10
10
100
50
85
25
—
Condition
10 MHz
Max
150
—
—
—
150
—
—
—
—
150
—
—
200
—
—
0.6
150
—
—
—
—
—
200
40
200
—
—
—
—
—
—
180
Unit
ns
ns
ns
t
ns
ns
ns
t
t
ns
t
t
ns
ns
ns
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
Scyc
Test Conditions
Fig. 23.13
Fig. 23.14
Fig. 23.15
Fig. 23.17
Fig. 23.16
Fig. 23.18
Fig. 23.19
Fig. 23.20
Fig. 23.21
Fig. 23.22
Fig. 23.23
581
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