HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 334

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

13.3.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The receive procedure and operations in slave receive
mode are described below. See also figure 13.9.
1. Set bits MLS and WAIT in ICMR and bits MST, TRS, and ACK in ICCR according to the
2. A start condition output by the master device sets BBSY to 1 in ICSR.
3. After the slave device detects the start condition, if the first byte matches its slave address, at
4. Software clears IRIC to 0 in ICSR.
5. When ICDR is read, receiving of the next data starts.
Steps 4 and 5 can be repeated to receive data continuously. When a stop condition is detected (a
low-to-high transition of SDA while SCL is high), BBSY is cleared to 0 in ICSR.
302
User processing
SCL (master
output)
SCL (slave
output)
SDA (master
output
SDA (slave
output)
IRIC
operating mode. Set bit ICE in ICCR to 1, establishing slave receive mode.
the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the
same time, IRIC is set to 1 in ICSR. If IEIC is 1 in ICCR, a CPU interrupt is requested. The
slave device holds SCL low from the fall of the receive clock until it has read the data in
ICDR.
Slave Receive Operation
Start condition
Figure 13.9 Operation Timing in Slave Receive Mode
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
1
(MLS = WAIT = ACK = ACKB = 0)
2
3
4
5
6
Bit 1 Bit 0
4. Clear IRIC
7
8
Interrupt
request
A
9
5. Read ICDR
Bit 7
1