HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 317

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

13.2
13.2.1
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. Transmitting is started by writing data in
ICDR. Receiving is started by reading data from ICDR.
ICDR is also used as a shift register, so it must not be written or read until data has been
completely transmitted or received. Read or write access while data is being transmitted or
received may result in incorrect data.
The ICDR value is undefined after a reset and in hardware standby mode.
13.2.2
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SAR match the upper 7 bits of the first byte received after a start condition, the
chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR. SAR can be written and read only when the ICE bit is cleared to 0 in ICCR.
SAR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,
differing from the addresses of other slave devices connected to the I
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Register Descriptions
I
Slave Address Register (SAR)
2
C Bus Data Register (ICDR)
ICDR7
SVA6
R/W
R/W
—
7
7
0
ICDR6
SVA5
R/W
R/W
—
6
6
0
ICDR5
SVA4
R/W
R/W
—
5
5
0
ICDR4
SVA3
R/W
R/W
—
4
4
0
ICDR3
SVA2
R/W
R/W
—
3
3
0
2
C bus.
ICDR2
SVA1
R/W
R/W
—
2
2
0
ICDR1
SVA0
R/W
R/W
—
1
1
0
ICDR0
R/W
R/W
FS
—
0
0
0
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