HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 293

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clock
In asynchronous mode it is possible to select either an internal clock created by the on-chip baud
rate generator, or an external clock input at the SCK pin. The selection is made by the C/A bit in
the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR).
Refer to table 12.8.
If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate.
If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is
used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises
at the center of the transmit data bits. Figure 12.3 shows the phase relationship between the output
clock and transmit data.
Transmitting and Receiving Data
SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to 0
in the serial control register (SCR), then initialize the SCI following the procedure in figure 12.4.
Note: When changing the communication mode or format, always clear the TE and RE bits to 0
before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and
initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize
the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their
previous contents.
When an external clock is used, the clock should not be stopped during initialization or
subsequent operation. SCI operation becomes unreliable if the clock is stopped.
Figure 12.3 Phase Relationship between Clock Output and Transmit Data
0
D0
D1
D2
D3
(Asynchronous Mode)
One frame
D4
D5
D6
D7
0/1
1
1
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