MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 752
MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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EMAC
ENABLE_TEST_CTRL instruction 31-8
End-of-frame (EOF) 25-12
EPORT
Error counters 25-13
Error interrupt (ERRINT) bit 25-27
Ethernet
Index-4
I
I
JTAG and boundary scan timing 33-25
maximum ratings 33-1
MII async inputs signal timing 33-23
MII receive signal timing 33-21
MII serial management channel timing 33-23
MII transmit signal timing 33-22
PLL specifications 33-4
QADC absolute maximum ratings 33-8
QADC operating conversion specifications 33-10
QADC operating electrical specifications 33-9
QSPI AC timing specifications 33-24
QSPI specifications 33-24
reset and configuration override timing 33-19
SDRAM timing 33-17
thermal 33-2
data representation 3-14
instructions
memory map 3-3
opcodes 3-14
operation
registers
low-power modes 7-10
memory map 11-3
overview 11-1
programming model 7-1
registers
address recognition 17-35
block diagram 17-2
buffer descriptors
collision handling 17-42
2
2
C input/output timing specifications 33-20
C output timing between SCL and SDA 33-20
execution timing 3-13
summary 3-12
fractional 3-10
BDM accesses 30-33
mask (MASK) 3-5
status (MACSR) 3-3
data direction (EPDDR) 11-4
flag (EPFR) 11-6
pin assignment (EPPAR) 11-3
pin data (EPPDR) 11-6
port data (EPDR) 11-5
port interrupt enable (EPIER) 11-5
receive (RxBD) 17-27
transmit (TxBD) 17-29
,
11-1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
electrical characteristics
errors
frame reception 17-35
frame transmission 17-33
hash table 17-38
initialization 17-30
operation
registers
MII receive signal timing 33-21
MII serial management channel timing 33-23
MII transmit signal timing 33-22
handling 17-42
reception
transmission
10 Mbps 7-Wire 17-4
10 Mbps and 100 Mbps MII 17-32
full duplex 17-4
half duplex 17-4
loopback 17-42
low-power modes 7-9
control (ECR) 17-12
descriptor group upper/lower address
descriptor individual upper/lower (IAUR/IALR) 17-20
descriptor individual upper/lower address
FIFO receive bound (FRBR) 17-22
FIFO receive start (FRSR) 17-23
FIFO transmit FIFO watermark (TFWR) 17-22
interrupt event (EIR) 17-9
interrupt mask (EIMR) 17-10
MIB control (MIBC) 17-16
MII management frame (MMFR) 17-13
MII speed control (MSCR) 17-15
opcode/pause duration (OPD) 17-19
physical address low (PALRn) 17-18
physical address low/high (PALR, PAUR) 17-18
receive buffer size (EMRBR) 17-24
receive control (RCR) 17-16
receive descriptor active (RDAR) 17-11
receive descriptor ring start (ERDSR) 17-23
transmit buffer descriptor ring start (ETSDR) 17-24
transmit control (TCR) 17-17
transmit descriptor active (TDAR) 17-12
CRC 17-44
frame length 17-44
non-octet 17-43
overrun 17-43
truncation 17-44
attempts limit expired 17-43
heartbeat 17-43
late collision 17-43
underrun 17-43
(GAUR/GALR) 17-21
(IAUR/IALR) 17-20
,
17-41
,
17-32
Freescale Semiconductor
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