MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 352
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 352 of 766
- Download datasheet (9Mb)
Fast Ethernet Controller (FEC)
When the transmitter pauses due to receiver/microcontroller pause frame detection, TCR[TFC_PAUSE]
may remain set and cause the transmission of a single pause frame. In this case, the EIR[GRA] interrupt
is not asserted.
17.5.12 Inter-Packet Gap (IPG) Time
The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After completing a
transmission or after the backoff algorithm completes, the transmitter waits for carrier sense to be negated
before starting its 96 bit time IPG counter. Frame transmission may begin 96 bit times after carrier sense
is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times, it
is ignored and a collision occurs.
The receiver accepts back-to-back frames with a minimum spacing of at least 28 bit times. If an
inter-packet gap between receive frames is less than 28 bit times, the receiver may discard the following
frame.
17.5.13 Collision Managing
If a collision occurs during frame transmission, the Ethernet controller continues the transmission for at
least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the collision occurs during the
preamble sequence, a JAM pattern is sent after the end of the preamble sequence.
If a collision occurs within 512 bit times (one slot time), the retry process is initiated. The transmitter waits
a random number of slot times. If a collision occurs after 512 bit times, then no retransmission is performed
and the end of frame buffer is closed with a Late Collision (LC) error indication.
17.5.14 MII Internal and External Loopback
Internal and external loopback are supported by the Ethernet controller. In loopback mode, both of the
FIFOs are used and the FEC actually operates in a full-duplex fashion. Internal and external loopback are
configured using combinations of the RCR[LOOP, DRT] and TCR[FDEN] bits.
Set FDEN for internal and external loopback.
For internal loopback, set RCR[LOOP] and clear RCR[DRT]. FEC_TXEN and FEC_TXER do not assert
during internal loopback. During internal loopback, the transmit/receive data rate is higher than in normal
operation because the transmit and receive blocks use the internal bus clock instead of the clocks from the
external transceiver. This causes an increase in the required system bus bandwidth for transmit and receive
data being DMA’d to/from external memory. It may be necessary to pace the frames on the transmit side
and/or limit the size of the frames to prevent transmit FIFO underruns and receive FIFO overflows.
For external loopback, clear RCR[LOOP] and RCR[DRT], and configure the external transceiver for
loopback.
17.5.15 Ethernet Error-Managing Procedure
The Ethernet controller reports frame reception and transmission error conditions using the MIB block
counters, the FEC RxBDs, and the EIR register.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
17-42
Freescale Semiconductor
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